Harris Tapped for 40 Under 40 Awards

Dateline

Images

Joyelle Harris was one of 40 individuals from the metro Atlanta area who were honored at the 2017 Atlanta Business Chronicle 40 Under 40 Awards. An academic professional in the Georgia Tech School of Electrical and Computer Engineering (ECE), Harris and her fellow honorees were recognized at an event held at the Foundry at Puritan Mill on November 8.

The 40 Under 40 Awards honor young movers and shakers who are making a mark in their industries and leading in their communities. Harris was specifically recognized for her work as director of the Engineering for Social Innovation (ESI) Center and as co-director of the Grand Challenges Scholars Program, both of which are initiatives housed in the Georgia Tech College of Engineering (CoE), and for her work as executive director of the Council of Schools and Services for the Blind. She was also honored for her prior contributions to the community through her work at Oak Ridge National Labs, Exponent, and Intel.   

Through ESI, Harris enables hundreds of students each year to use their coursework and technical skills for significant, positive social impact in community projects throughout Atlanta and all over the world. In her ESI work, she empowers her community partners by incorporating their needs and desires into solutions that are sustainable and desirable. In the CoE Grand Challenges Scholars Program, Harris works with students who want to tackle today’s science, engineering, and technology challenges in areas like cybersecurity and global access to healthcare.

Harris was also recognized for her work with several student organizations, including Engineers Without Borders, which helps to improve the infrastructure of communities throughout the developing world, and Enterprise to Empower, an organization that helps students launch nontraditional, impact careers.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Spring 2018 IEN Seed Grant Winners Announced

Dateline

Images

Fall 2017 Seed Grant Winner at the IEN User Poster Session on May 21, 2018 - Arith Rajapaks

The Institute for Electronics and Nanotechnology at Georgia Tech has announced the winners for the 2018 Spring Seed Grant Awards. The primary purpose of the IEN Seed Grant is to give first or second year graduate students in various disciplines working on original and un-funded research in micro- and nano-scale projects the opportunity to access the most advanced academic cleanroom space in the Southeast. In addition to accessing the high-level fabrication, lithography, and characterization tools in the labs, the students will have the opportunity to gain proficiency in cleanroom and tool methodology and to use the consultation services provided by research staff members of the IEN Advanced Technology Team.  In addition, the Seed Grant program gives faculty with novel research topics the ability to develop preliminary data in order to pursue follow-up funding sources.

Over the course of five years, this grant program has seeded forty-five projects with forty-nine students working in ten different schools in COE and COS, as well as the Georgia Tech Research Institute and 2 external projects.

The 4 winning projects, from a diverse group of engineering disciplines, were awarded a six-month block of IEN cleanroom and lab access time. In keeping with the interdisciplinary mission of IEN, the projects that will be enabled by the grants include research in materials, biomedicine, energy production, and microelectronics packaging applications.

The Spring 2018 IEN Seed Grant Award winners are:

  • Jiang Chen (PI Ben Wang - MSE): Validation and Characterization of Living Cell Grafting on Polycaprolactone Fibers for Textile Tissue Engineering
  • Fatima Chrit (PI Alexander Alexeev - ME): Microfluidic Adhesion-based Sorting of Biological Cells
  • Zifei Sun (PI Gleb Yushin - MSE): FeOx Coated FeF3-C Nanofibers as Free-standing Cathodes for Sodium- Ion Batteries
  • Ting Wang (PI Xing Xie - Civil and Environmental Engineering): Development of Lab-on-a-Chip Devices for the Mechanisms Study of Cell Transportation and Bacteria Inactivation in a Non-Uniform Electric Field

Awardees will present the results of their research efforts at the annual IEN User Day in 2019.

Coyle Tapped for SUNY-Industry Conference Award

Dateline

Images

Edward J. Coyle presented with award at SUNY Industry Conference and Showcase

Edward J. Coyle received the “Advancing Civic Engagement and Socially Beneficial Science and Engineering” Award at the SUNY-Industry Conference and Showcase: Science and Engineering for Social Good. The conference was held June 3-5, 2018 at Stony Brook, New York. 

Conference themes included areas of critical civic and social importance: energy and environment, health, broadening participation in STEM (human resource development), education and the technological workforce, integrating STEM and the arts and humanities, infrastructure development, technology and security, social media, and data science.

Coyle took part in this conference as one of the plenary speakers and represented the Vertically Integrated Projects (VIP) Program at Georgia Tech. He was nominated for this award by David Ferguson who is a Distinguished Service Professor of Technology and Society and Applied Mathematics and Statistics at Stony Brook University and was presented the award by Samuel Stanley, the president of Stony Brook University. 

Coyle has been a member of the Georgia Tech School of Electrical and Computer Engineering (ECE) faculty since 2008. He holds the John B. Peatman Distinguished Professorship and is a Georgia Research Alliance Eminent Scholar. Coyle leads the Arbutus Center for the Integration of Research and Education and the Vertically Integrated Projects Program (VIP), which develop strategies for systemic reform of higher education in all disciplines. 

VIP unites undergraduate education and faculty research in a team-based context and involves faculty from almost all colleges at Georgia Tech and the Georgia Tech Research Institute. Undergraduate VIP students earn academic credits, while faculty and graduate students benefit from the design/discovery efforts of their teams. VIP research projects are multidisciplinary and range from robotics applications of many kinds to intelligent transportation systems to automobile design to brain trauma assessment.

Cutline for photograph (above): Edward J. Coyle is presented with the Advancing Civic Engagement and Socially Beneficial Science and Engineering” Award by David Ferguson (left) and Stony Brook University President google.comSamuel Stanley (right)

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Neuroscientists Team with Engineers to Explore How the Brain Controls Movement

Dateline

Images

Muhannad Bakir (far left) and Emory's Samuel Sober (far right) combined forces for the project. The work will be led by post-doctoral fellows in their labs, Georgia Tech's Muneeb Zia (center left) and Emory's Bryce Chung (center right).
Recording device for muscles

This article was written by Carol Clark, senior science communicator at Emory University and editor of eScience Commons

Scientists have made remarkable advances into recording the electrical activity that the nervous system uses to control complex skills, leading to insights into how the nervous system directs an animal’s behavior. 

“We can record the electrical activity of a single neuron, and large groups of neurons, as animals learn and perform skilled behaviors,” says Sam Sober, an associate professor of biology at Emory University who studies the brain and nervous system. “What’s missing,” he adds, “is the technology to precisely record the electrical signals of the muscles that ultimately control that movement.”

The Sober lab is now developing that technology through a collaboration with the lab of Muhannad Bakir, a professor in Georgia Tech’s School of Electrical and Computer Engineering. The researchers recently received a $200,000 Technological Innovations in Neuroscience Award from the McKnight Foundation to create a device that can record electrical action potentials, or “spikes” within muscles of songbirds and rodents. The technology will be used to help understand the neural control of many different skilled behaviors to potentially gain insights into neurological disorders that affect motor control.

“Our device will be the first that lets you record populations of spikes from all of the muscles involved in controlling a complex behavior,” Sober says. “This technique will offer unprecedented access to the neural signals that control muscles, allowing previously impossible investigations into how the brain controls the body.”

“By combining expertise in the life sciences at Emory with the engineering expertise of Georgia Tech, we are able to enter new scientific territory,” Bakir says. “The ultimate goal is to make discoveries that improve the quality of life of people.” 

The Sober lab previously developed a prototype device — electrodes attached to flexible wires — to measure electrical activity in a breathing muscle used by Bengalese finches to sing. The way birds control their song has a lot in common with human speech, both in how it is learned early in life and how it is produced in adulthood. The neural pathways for birdsong are also well known, and restricted to that one activity, making birds a good model system for studying nervous system function.

“In experiments using our prototype, we discovered that, just like in brain cells, precise spike timing patterns in muscle cells are critical for controlling behavior — in this case breathing,” Sober says.

The prototype device, however, is basic. Its 16 electrodes can only record activity from a single muscle — not the entire ensemble of muscles involved in birdsong. In order to gain a fuller picture of how neural signals control movement, neuroscientists need a much more sophisticated device.

The McKnight funding allowed Sober to team up with Bakir. Their goal is to create a micro-scale electromyography (EMG) sensor array, containing more than 1,000 electrodes, to record single-cellular data across many muscles. 

The engineering challenges are formidable. The arrays need to be flexible enough to fit the shape of small muscles used in fine motor skills, and to change shape as the muscles contract. The entire device must also be tiny enough not to impede the movement of a small animal.

“Our first step is to build a flexible substrate on the micro-scale that can support high-density electrodes,” Bakir says. “And we will need to use microchips that work in parallel with 1,000 electrodes, and then attach them to that substrate.”

To meet that challenge, the Bakir lab will create a 3D integrated circuit. “Essentially, it’s building a miniature skyscraper of electrical circuits stacked vertically atop one another,” Bakir says. This vertical design will allow the researchers to minimize the size of the flexible substrate.

“To our knowledge, no one has done what we are trying to do in this project,” Bakir says. “That makes it more difficult, but also exciting because we are entering new space.”  

The Sober lab will use the new device to expand its songbird vocalization studies. And it will explore how the nervous system controls the muscles involved when a mouse performs skilled movements with its forelimbs. 

An early version of the technology will also be shared with collaborators of the Sober lab at three different universities. These collaborators will further test the arrays, while also gathering data across more species.

“We know so little about how the brain organizes skilled behaviors,” Sober says. “Once we perfect this technology, we will make it available to researchers in this field around the world, to advance knowledge as rapidly as possible.”

The mission of the McKnight Foundation’s Technological Innovations in Neuroscience Award, as described on its website, is “to bring science closer to the day when diseases of the brain and behavior can be accurately diagnosed, prevented and treated.”

Full cutline information for photos

Top photo: The labs of Georgia Tech's Muhannad Bakir (far left) and Emory's Samuel Sober (far right) combined forces for the project. The work will be led by post-doctoral fellows in their labs, Georgia Tech's Muneeb Zia (center left) and Emory's Bryce Chung (center right). Photos by Ann Watson, Emory Photo/Video.

Second photo: A prototype of the proposed device has 16 electrodes that can record data from a single muscle. The McKnight Award will allow the researchers to scale up to a device with more than 1,000 electrodes that can record from 10 or more muscles.

Krishna to Have Two Papers Featured in IEEE Micro Top Picks Issue

Dateline

Images

Tushar Krishna will have two of his recent research papers featured in the IEEE Micro“Top Picks from Computer Architecture Conferences,” to be published in the May/June 2019 issue. One paper was selected as an IEEE Micro Top Pick, and another paper was selected as an Honorable Mention. 

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. He has been on the faculty since 2015. 

Every year, IEEE Micro publishes this special issue, which recognizes the year’s top papers that have potential for long-term impact. In order for a paper to be chosen as a top pick, it must first have been accepted in a major computer architecture conference that year. Out of 123 top pick submissions in 2018, 12 were selected as Top Picks and 11 were selected as Honorable Mentions. 

IEEE Micro Top Pick

Krishna’s paper that was selected as a Top Pick is entitled “Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom.” The paper was published at the 45th International Symposium on Computer Architecture (ISCA), held June 2-6, 2018 in Los Angeles, California. Krishna’s coauthors are his recently graduated M.S. student, Aniruddh Ramrakhyani, and Paul Gratz, an ECE associate professor at Texas A&M University.

All high-performance computers today are built by connecting many processors together. These could be cores on a single-chip inside a smartphone or laptop, or servers inside a supercomputer or datacenter. A key challenge in designing the interconnection network connecting these processors is that of “deadlocks”. A deadlock is a scenario where a set of packets is stuck indefinitely and cannot move forward because they form a cyclic dependence. An analogy is that of a traffic jam in road networks where each car waits for the car in front of it to move, but no car can move if they end up forming a cycle. The traditional approaches to avoid deadlocks either restricts routes (leading to lower performance) or adds more queues (leading to more area and power). Unfortunately, paying one of these two expenses is unavoidable today since a deadlock can bring the whole system to a standstill and has to be avoided for functional correctness of any interconnection network.

In this paper, Krishna and his co-authors challenge the theoretical notion of viewing deadlocks as a resource (in this case queues) dependence problem, and view it instead as a lack of coordination between distributed packets. They demonstrate that enabling every packet to move forward at exactly the same time can help them all move forward and get out of the deadlock. Imagine the same traffic jam as before, but every car in the jam agreeing to move forward at exactly the same time to avoid any collisions. This was the first work to show a deadlock-free interconnection network with fully adaptive routing, without any routing restrictions, with only a single queue at every router port.

IEEE Micro Honorable Mention

Krishna’s paper that was selected as an Honorable Mention is entitled “MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.” The paper was published at the 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), held March 24-28, 2018 in Williamsburg, Virginia. Krishna’s coauthors are his Ph.D. students, Hyoukjun Kwon and Ananda Samajdar.

Machine Learning (ML) and Artificial Intelligence (AI) are becoming ubiquitous. Deep Neural Networks (DNN) have demonstrated highly promising results across applications like computer vision, speech recognition, language translation, recommendation systems, and games. The computational complexity of DNNs and a need for high energy-efficiency has led to a surge in research on hardware accelerators. These AI accelerators are designed for keeping the target DNN algorithm in mind, and use custom datapaths and memory hierarchies to provide 10-1000x better performance or energy-efficiency than traditional CPUs and GPUs. Almost every major company today is building its own version of an AI accelerator. However, a key challenge today is that AI/ML algorithms are evolving at an extremely rapid rate - almost daily, while designing and taping out a hardware chip takes millions of dollars, and replacing these chips every time the algorithm changes is not practical. Thus, an open question today is how to design an accelerator chip that can be built and deployed (on smartphones and/or datacenters) and will be able to run both current and future algorithms efficiently, without having to be replaced frequently.

In their paper, Krishna and his students address this issue by adding lightweight, non-blocking, and reconfigurable interconnects within a DNN accelerator called MAERI. They demonstrate that almost any DNN model can be mapped while utilizing close to 100 percent of the accelerator’s compute resources, by simply reconfiguring the proposed interconnects appropriately. This makes the MAERI approach future-proof to innovations across DNN models and dataflow/mapping techniques.

WCP 2019 Awards Announced

Subtitle

Annual faculty and student awards announced at April 25 ceremony.

Dateline

Krishna Chosen for Facebook Research Faculty Award

Dateline

Images

Tushar Krishna has been chosen as one of the recipients of Facebook Research's Faculty Award for AI System Hardware/Software Co-Design. Krishna was among the eight winners who were selected from 88 worldwide submissions.  

The title of Krishna’s award-winning project is “ML-Driven HW-SW Co-Design of Efficient Tensor Core Architectures.” In this project, co-design implies simultaneous design and optimization of several aspects of the system, including hardware and software, to achieve a set target for a given system metric, such as throughput, latency, power, size, or any combination these factors. 

Artificial intelligence (AI) and deep learning have been particularly amenable to such co-design processes across various parts of the software and hardware stack, leading to a variety of novel algorithms, numerical optimizations, and AI hardware. Krishna’s proposal focuses on creating an automated machine learning (ML)-driven closed-loop system to generate custom AI hardware platforms for the target algorithms and/or performance/energy constraints using a library of lego-like heterogeneous hardware building blocks.

Krishna has been an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. He and his team focus on architecting next-generation intelligent computer systems and interconnection networks for emerging application areas such as machine learning. Krishna has received a Google Faculty Research Award and an NSF CISE Research Initiation Initiative Award. He recently had one of his papers selected as an IEEE Micro Top Pick from computer architecture conferences and a second paper was selected as an Honorable Mention; Krishna’s work will be acknowledged in the May/June 2019 issue of IEEE Micro.

VIP Consortium Receives 2019 ABET Innovation Award

Dateline

Images

Edward J. Coyle

The Vertically Integrated Projects (VIP) Consortium has been selected for the 2019 ABET Innovation Award “for community-building around and dissemination of the Vertically Integrated Projects model, a scalable, cost-effective approach to undergraduate research adopted by 35 colleges and universities around the world.”

The ABET Innovation Award recognizes vision and commitment that challenge the status-quo in technical education. It honors individuals, organizations, or teams that are breaking new ground by developing and implementing innovation into their ABET-accredited programs. 

According to the ABET website, true innovation is hard to define, but easy to identify. This award distinguishes programs or individuals that have brought a significant innovation to STEM education in areas like curriculum development, laboratory experiences, teaching methodologies, cross-disciplinary programs, and experiential learning–almost anything designed and proven to improve a student’s educational experience.

The Vertically Integrated Projects (VIP) Program is a transformative approach to enhancing higher education by engaging undergraduate and graduate students in ambitious, long-term, large-scale, multidisciplinary project teams that are led by faculty. In VIP, teams of undergraduate students–from various years, disciplines, and backgrounds–work with faculty and graduate students in their areas of scholarship and exploration. Undergraduate students earn academic credit for their work and have direct experience with the innovation process, while faculty and graduate students benefit from the extended efforts of their teams.  

The VIP Program at Georgia Tech is led by Edward J. Coyle, who developed the VIP concept. As of Spring 2019, there were 70 VIP teams at Georgia Tech with more than 1,100 students enrolled. While the program originated in the School of Electrical and Computer Engineering, students from each of the six colleges on campus participate. Student applications are currently being accepted for Fall 2019 at www.vip.gatech.edu

Under Coyle’s leadership, the VIP Program has spread to dozens of universities around the world. The VIP Consortium (www.vip-consortium.org) is an alliance of institutions that have successfully implemented the VIP Program and engage in collaborative efforts to continue to improve and disseminate the model. To date, 35 institutions across the globe have joined the VIP Consortium, and thousands of students participate in VIP programs on these campuses each semester. Each partner site adapts the model to its own unique environment, using an essential set of program elements and specialized tools for program management and assessment. 

ABET (www.abet.org) is the professional accreditation agency providing leadership and quality assurance in applied science, computing, engineering, and engineering technology education. The ABET Innovation Award is given to a nominee selected by their peers. The president of ABET annually appoints a special committee for review of nominations for this award. The Awards Committee’s recommendations are presented to the members of the Board of Delegates for concurrence.

Awards will be presented at the 2019 ABET Awards Celebration on Friday, November 1 at the Hilton in Baltimore, Maryland.

For more information about the VIP Consortium and VIP @ Georgia Tech, contact:

Edward J. Coyle                                                                                

Director, VIP @ Georgia Tech & VIP Consortium

John B. Peatman Distinguished Professor; and Georgia Research Alliance Eminent Scholar 

School of Electrical and Computer Engineering

Georgia Institute of Technology                                                         

ejc@gatech.edu

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Krishna Named to ON Semiconductor Junior Professorship

Dateline

Images

Tushar Krishna has been appointed to the ON Semiconductor Junior Professorship, effective September 1, 2019. A professorship for untenured faculty members in the Georgia Tech School of Electrical and Computer Engineering (ECE), this position was previously held by ECE Professor Arijit Raychowdhury. 

Krishna joined the ECE faculty in August 2015, after working as a postdoctoral researcher at MIT and a research engineer at Intel in Hudson, Massachusetts. He is a member of the Computer Systems and Software technical interest group and holds an adjunct faculty appointment with Tech’s School of Computer Science. 

Krishna’s research spans the areas of computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators. Working amongst these research areas, he and his team of seven graduate students in the Synergy Lab focus on optimizing data movement in modern computing systems. Krishna has graduated four master’s degree students and has also had several undergraduate researchers working in his lab. An excellent classroom instructor, he teaches Advanced Computer Architecture; Architecture, Concurrency, and Energy in Computation; Interconnection Networks; and Hardware Accelerators for Machine Learning.

Krishna received the B.Tech. degree in Electrical Engineering with honors from the Indian Institute of Technology Delhi in 2007, the M.S.E. degree in Electrical Engineering from Princeton University in 2009, and the Ph.D. degree in Electrical Engineering and Computer Science from MIT in 2014. 

Krishna has published more than 50 refereed journal and conference papers. In 2018, he won the NSF CISE Research Initiation Initiative Award, and in 2019, he won both the Google Faculty Research Award and Facebook Research’s Faculty Award for AI System Hardware/Software Co-Design. Earlier this year, Krishna had one of his papers selected as an IEEE Micro Top Pick and a second paper was chosen as an Honorable Mention in the May/June 2019 issue of the journal. 

Nasir, Raychowdhury Selected for Top Pick Paper in Hardware and Embedded Security

Dateline

Images

Saad Bin Nasir

A paper coauthored by Saad Bin Nasir and Arijit Raychowdhury has been selected as a “Top Pick Paper in Hardware and Embedded Security.” Both of them are affiliated with the Georgia Tech School of Electrical and Computer Engineering (ECE); Nasir is a recent ECE Ph.D. graduate and Raychowdhury is a professor in the School and served as Nasir’s advisor.  

The “top picks” in hardware security represent the top 10 most impactful papers that have been published in the area in the last six years, from 2013 to 2018. Top pick papers span a gamut of topics in hardware, microarchitecture, and embedded security from leading conferences. They are selected from conference and journal papers that have appeared in leading hardware security conferences, including but not limited to DAC, DATE, ICCAD, HOST, VLSI Design, CHES, ETS, VTS, ITC, IEEE S&P, Euro S&P, Usenix Security, ASIA CCS, NDSS, ISCA, HASP, MICRO, ASPLOS, HPCA, ACSAC, and ACM CCS. 

Nasir’s top-pick paper is titled “High Efficiency Power Side-Channel Attack Immunity using Noise Injection in Attenuated Signature Domain” and had previously won the best paper award in the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) in 2017. This paper proposed a novel power management technique that reduces side channel leakage in cryptographic engines. The work was done in collaboration with researchers from Purdue University and continues to have a significant impact in the community. Parts of the design have been adopted by Intel and Qualcomm as a part of their hardware-security roadmap. 

Nasir graduated with his Ph.D. in December 2017 while working in the Integrated Circuits and Systems Research Lab under the advisement of Raychowdhury. Nasir is currently a researcher in Qualcomm’s Corporate Research Division in San Diego, California.

Subscribe to Student Research