Khan Wins NSF CAREER Award

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Asif Khan

Asif Khan has been named as a recipient of the NSF CAREER Award. He is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and also holds a courtesy appointment in the School of Materials Science and Engineering.

The title of Khan’s award is “Antiferroelectric Negative Capacitance Transistors for Ultra-low Power Computing,” and it will start on March 15, 2021 and end on February 28, 2026. 

Today's society is experiencing an unprecedented growth of its digital footprint – be it in the form of uploading a photo on Facebook, live-streaming a teaching module to a massive global audience on YouTube, or commandeering a revolution via Twitter. This convenience of modern computing, however, comes with a steep cost in terms of energy use and environmental impact. Today, the global information infrastructure, such as data centers, emit as much greenhouse gases as that of the state of Nevada or a country, such as The Netherlands or Malaysia, and constitute around 1 percent of world-wide electricity demand. According to scientific estimates, this fraction may increase to a double digit percentage in the next 15-20 years. 

At the core of this predicament lies the fact that the fundamental building blocks of digital hardware – the transistors – have long been overdue for a prime upgrade in terms of their energy efficiencies. The proposed research aims to explore an energy-efficient transistor concept – known as a negative capacitance field-effect transistor, using a new class of materials called antiferroelectric oxides. 

Khan joined the ECE faculty in 2017. His research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices, in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/data-centric applications. Khan’s Ph.D. work led to the proof-of-concept demonstration of the negative capacitance phenomenon in ferroelectric materials, which can reduce the power dissipation in electronic devices below the ‘fundamental’ thermodynamic limit. This culminated in the initial development of the field of negative capacitance.

Khan has published 2 book chapters and 70 journal and peer-reviewed conference publications, and he has given 20 invited talks and tutorials at premier microelectronics and ferroelectric conferences. Khan currently has one patent pending at Intel. 

Khan’s awards include the NSF CAREER award (2021), Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). His group at Georgia Tech consists of six Ph.D. students and three research engineers, many of whom won Institute-level and international awards, including an IEEE Electron Devices Society (EDS) Masters Student Fellowship (2020). Khan’s research is supported by the National Science Foundation, the Defense Advanced Research Projects Agency, the Semiconductor Research Corporation, and Intel Corporation. 

Khan has also developed a graduate course, ECE 8863A Quantum Computing Devices and Hardware, as a part of the campus wide response to the national prioritization of quantum computing, known as the National Quantum Initiative Act (NQIA) that was signed by the U.S. president in 2018. Khan recently received the Class of 1934 CIOS Honor Roll award for excellence in teaching this course in Fall 2020. 

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Four Georgia Tech Faculty Named IEEE Fellows

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Jaydev Desai
Four Georgia Tech faculty members were named IEEE Fellows, effective January 1, 2018. They are Jaydev Desai, a professor in the Wallace H. Coulter Department of Biomedical Engineering (BME); Saibal Mukhopadhyay and Justin Romberg, both professors in the School of Electrical and Computer Engineering (ECE); and Kevin James “Jim” Sangston, a senior research engineer in the Georgia Tech Research Institute (GTRI).
Saibal Mukhopadhyay has been an assistant professor in ECE since 2007.
Kevin James "Jim" Sangston

Four Georgia Tech faculty members were named IEEE Fellows, effective January 1, 2018. They are Jaydev Desai, a professor in the Wallace H. Coulter Department of Biomedical Engineering (BME); Saibal Mukhopadhyay and Justin Romberg, both professors in the School of Electrical and Computer Engineering (ECE); and Kevin James “Jim” Sangston, a senior research engineer in the Georgia Tech Research Institute (GTRI).

The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement.

Desai is being recognized “for contributions to medical and swarm robotics.” A BME faculty member since 2016, he also serves as associate director of the Institute for Robotics and Intelligent Machines and as director of the newly launched Georgia Center for Medical Robotics. Desai’s research interests are primarily in image-guided surgical robotics, cancer diagnosis at the micro-scale, and rehabilitation robotics. Before joining Georgia Tech, Desai was a professor in the Department of Mechanical Engineering at the University of Maryland, College Park.

Mukhopadhyay is being recognized “for contributions to energy-efficient and robust computing systems design.” An ECE faculty member since 2007, he leads the Gigascale Reliable Energy Efficient Nanosystem (GREEN) Lab, where he and his current team of 12 Ph.D. students develop smart machines that are able to generate usable information from real-time data for diverse applications - from self-powered sensors to mobile phones to high-performance servers. Mukhopadhyay’s team explores algorithmic principles to make these systems energy-efficient, robust, and secure, and pursue their experimental demonstration in silicon. 

Romberg is being recognized “for contributions to compressive sensing.” An ECE faculty member since 2006, he is the School’s associate chair for Research and holds the Schlumberger Professorship. In addition, Romberg serves as associate director for the Center for Machine Learning. He conducts research that is on the interface between signal processing, applied harmonic analysis, and optimization. Romberg and his current team of six Ph.D. students are interested in both the mathematical theory and real-world implementation of algorithms to make difficult processing tasks much easier.

Sangston is being recognized “for contributions to coherent detection of radar signals in clutter.” He initially came to GTRI from the U.S Naval Research Laboratory in 1996. His research in target detection in difficult clutter environments from the mid-1990s up till the present time has been a fruitful source of ideas and motivation for many investigators pursuing advanced research on radar target detection problems throughout the world. He currently works in the Sensors and Electromagnetic Applications Laboratory (SEAL), where he conducts research that seeks to combine advanced geometric and algebraic ideas to solve challenging radar signal processing problems. 

The IEEE is the world’s leading professional association for advancing technology for humanity. Through its 400,000-plus members in 160 countries, the association is a leading authority on a wide variety of areas ranging from aerospace systems, computers and telecommunications to biomedical engineering, electric power, and consumer electronics.

Dedicated to the advancement of technology, the IEEE publishes 30 percent of the world’s literature in the electrical and electronics engineering and computer science fields, and has developed more than 1,300 active industry standards.  The association also sponsors or co-sponsors nearly 1,700 international technical conferences each year.  To learn more about IEEE or the IEEE Fellow Program, please visit www.ieee.org.

Li Honored with IEEE Best Paper Award

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Geoffrey Ye Li has been named the recipient of the 2017 IEEE Donald G. Fink Overview Paper Award, which is given by the IEEE Signal Processing Society.

This award recognizes a journal article that has had substantial impact over several years on a subject related to the Society’s technical scope. Li will be presented with this award at the 2018 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), to be held April 15-20 in Calgary, Alberta, Canada.

The title of the award-winning paper is “An Overview of Massive MIMO: Benefits and Challenges,” published in the IEEE Journal of Selected Topics in Signal Processing, volume 8, number 5 in October 2014. Massive MIMO wireless communications have attracted much attention for their potential to tremendously improve spectral and energy efficiency of networks using relatively simple processing. Techniques related to massive MIMO have been extensively investigated. As one of the first comprehensive surveys on massive MIMO, this overview article has served as an excellent reference and a starting point for readers interested in massive MIMO topics in the past several years. 

Li is a professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and has been on the faculty since 2000. His coauthors are Lu Lu, a Ph.D. graduate of Li’s research group–the Information Transmission and Processing Laboratory–and who now works with Intel in Portland, Oregon; A. Lee Swindlehurst, a professor in the Henry Samueli School of Engineering at the University of California, Irvine; Alexei Ashikhmin, distinguished member of the technical staff of Bell Labs in New Jersey; and Rui Zhang, an associate professor in the Department of ECE at the National University of Singapore.

Wang Tapped for DARPA Young Faculty Award

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Hua Wang has received a DARPA Young Faculty Award (YFA) for his research on mm-Wave power amplifiers with extreme bandwidth and energy efficiency.

A member of the Georgia Tech School of Electrical and Computer Engineering faculty since 2012, Wang holds the Demetrius T. Paris Junior Professorship and leads the Georgia Tech Electronics and Micro-System (GEMS) Lab. He has also received multiple prestigious academic awards, including the IEEE MTT-S Outstanding Young Engineer Award in 2017, Georgia Tech Sigma Xi Young Faculty Award in 2016, National Science Foundation (NSF) CAREER Award in 2015, Roger P. Webb ECE Outstanding Junior Faculty Member Award in 2015, and Lockheed Dean’s Excellence in Teaching Award in 2015, as well as many best paper awards in the field of solid-state circuits, systems, and microwave engineering. Wang is also a Distinguished Lecturer for the IEEE Solid-State Circuits Society for 2018 and 2019.

As millimeter-wave frequency applications have become prevalent in the commercial and Department of Defense markets, there is a rapidly growing need for advanced millimeter-wave solid-state power amplifier technologies that can support high energy efficiency, sufficient output power, and high-speed complex modulations. Moreover, high-efficiency amplifiers covering extremely wide bandwidth have become a necessity, particularly for frequency-agile massive Multiple-Input-Multiple-Output (MIMO) systems, such as multi-standard 5G wireless communication.

In this project, Wang will lead the fundamental research on a completely new class of extremely-wideband-yet-efficient power amplifiers over the frequency range of 30-100GHz. The key technology innovations include novel amplifier circuit topologies, hybrid use of silicon/non-silicon solid-state devices, and multi-mode amplifier operations.

This project will potentially achieve a new class of load modulation power amplifiers with an unprecedented combination of bandwidth, energy efficiency, and output power. Such amplifier technologies will eventually enable true “common-module front-ends” for reconfigurable transmitters and MIMO systems with "full-spectrum access" and digital beam-forming for wireless communication, radar, imaging, and spectrum sensing applications.

Krishna’s Research to be Featured in IEEE Micro Top Picks Issue

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Tushar Krishna will have one of his recent research papers featured in the IEEE Micro “Top Picks from Computer Architecture Conferences,” to be published in the May/June 2020 issue. 

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering, where he leads the Synergy Lab. This is the second year in a row that one of Krishna’s papers has been chosen as an IEEE Micro Top Pick.

Every year, IEEE Micro publishes this special issue, which recognizes the year’s top papers in computer architecture that have potential for long-term impact. In order for a paper to be considered for a top pick, it must first have been accepted in a major computer architecture conference that year and that have acceptance rates of ~18-22%. Out of 96 submissions this year, twelve were selected as "Top Picks." 

Krishna's paper was titled "Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach.” The co-authors were his Ph.D. student Hyoukjun Kwon; Vivek Sarkar, a professor from the School of Computer Science; Sarkar's Ph.D. student Prasanth Chatarasi; and two NVIDIA collaborators, Michael Pellauer and Angshuman Parashar. 

Deep Learning is being deployed at an increasing scale—across the cloud and IoT platforms—to solve complex regression and classification problems in image recognition, speech recognition, language translation, and many more fields, with accuracy close to and even surpassing that of humans. Tight latency, throughput, and energy constraints when running Deep Neural Networks (DNNs) have led to a meteoric increase in specialized hardware–known as accelerators–to run them.

Running DNNs efficiently is challenging for two reasons. First, DNNs today are massive and require billions of computations, and secondly, DNNs have millions of inputs/weights that need to be moved from memory to the accelerator chip which consumes orders of magnitude more energy than the actual computation. DNN accelerators try to address these two challenges by mapping these computations in parallel across hundreds of processing elements to improve performance and by reusing inputs/weights on-chip across multiple outputs to improve energy efficiency. Unfortunately, there can be trillions of ways of slicing and dicing the DNN (also known as “dataflow”) to map it over the finite compute and memory resources within an accelerator.

Krishna’s paper demonstrates a principled approach and framework called MAESTRO to estimate data reuse, performance, power, and area of DNN dataflows. MAESTRO enables rapid design-space exploration of DNN accelerator architectures and mapping strategies, depending on the target DNNs or domain (cloud or IoT). MAESTRO is available as an open-source tool at http://synergy.ece.gatech.edu/tools/maestro, and it has already seen adoption within NVIDIA, Facebook, and Sandia National Labs.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Mukhopadhyay Receives Intel Outstanding Researcher Award

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Saibal Mukhopadhyay has been an assistant professor in ECE since 2007.

Saibal Mukhopadhyay is a recipient of Intel’s 2019 Outstanding Researcher Award. He is one of seven researchers from around the world to receive this award who work in the areas of quantum computing, artificial intelligence, and other emerging innovative technologies. 

Mukhopadhyay is the Joseph M. Pettit Professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), and he leads the Gigascale Reliable Energy-Efficient Nanosystem (GREEN) Lab. He received the Intel Outstanding Researcher Award for his collaborative research on “Integrated Voltage Regulators for Power Attack Protection of Encryption Engines.”  

Modern system-on-chips (SoCs) ranging from high performance processors to smart phones to Internet-of-Things devices include on-chip encryption circuits. An encrypted message is secure as long as the key is a secret. But whenever an encryption engine operates, it dissipates power and generates electromagnetic emissions that depends on the value of the secret key. An adversary can “listen” to these signals and find out the secret key through statistical analysis. This problem is known as side channel analysis, and it is a critical threat to modern microelectronics. The traditional approaches to reduce this information leakage often increases energy consumption or slows down the circuit. 

In this collaborative project with Intel, Arvind Singh and Monodeep Kar, both former Ph.D. students in the GREEN Lab, and Mukhopadhyay have explored a new way to address this problem. The integrated voltage regulators are an essential component to improve energy-efficiency of modern SoCs. The GREEN lab team has demonstrated security-aware voltage regulators that, along with assisting in energy-management, also reduce information leakage from encryption engines. Their design makes it thousands (3000X) of times harder to attack a chip but adds minimal overhead.  

The project has led to multiple articles in top circuit conferences and journals, including the International Solid-State Circuits Conference, IEEE Journal of Solid-State Circuits, and IEEE Transactions on Power Electronics; many tutorials and invited presentations; and two Ph.D. theses. The work was also covered in IEEE Spectrum.

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