Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) partners with Notre Dame in $26 million multi-university research center developing next-generation computing technologies

Dateline

Images

John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.
Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology

In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.

With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).

Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) led by Profs. A. Raychowdhury and M. Swaminathan, deputy director and director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.

The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.

Profs. Raychowdhury (PI) and Swaminathan (co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.

“Our involvement in the ASCENT center provides us with unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof. Raychowdhury, the ON Semiconductor Jr. Associate Professor of VLSI Systems.

“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”

This is one of the largest JUMP centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies.  Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.

- Christa M. Ernst

EDA’s CAEML Grows More Humps: Al Expands Role in Design

Dateline

Images

John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.

The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.

Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.

“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”

Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.

After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.

Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."

Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).

“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”

https://www.eetimes.com/document.asp?doc_id=1332917

Yu to Receive Inaugural SRC Young Faculty Award

Dateline

Keywords

SRC

Images

Shimeng Yu

Shimeng Yu has been named as the recipient of the inaugural Semiconductor Research Corporation (SRC) Young Faculty Award. 

An associate professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), Yu will be presented with the award at the annual SRC TECHCON meeting, to be held September 9-10, 2019 in Austin, Texas. He is also a member of the Institute for Electronics and Nanotechnology. This new award is presented to an untenured full-time faculty member who is a principal investigator (PI) or co-principal investigator working on research that greatly enriches the SRC research agenda.

Yu has been a member of Tech’s ECE faculty since August 2018, where he leads the Laboratory for Emerging Devices and Circuits. Yu is involved in several SRC projects. 

  • Yu is a member of the Applications and Systems-Driven Center for Energy-Efficient Integrated NanoTechnologies (ASCENT), which is part of the SRC/DARPA Joint University Microelectronics Program. ASCENT's mission is to provide breakthrough advances in integrated nanoelectronics to sustain the promise of Moore’s Law. Led by the University of Notre Dame, along with 13 partner universities and 29 principal investigators, the Center is funded for $49 million over five years. Yu's specific research within ASCENT develops emerging nanoelectronic devices that emulate the synapses and neurons to build hardware platforms for machine learning and neuromorphic computing. 
  • He is a member of the SRC nanoelectronic COmputing REsearch (nCORE) program, in particular the Energy-Efficient Computing: From Devices to Architectures (E2CDA) program. In this effort, jointly funded with the National Science Foundation, Yu is developing a software simulation framework to benchmark the emerging device technology's impact on artificial intelligence across the layers from algorithms, computer architecture, and circuit and chip design down to devices and materials. 
  • Yu is a PI of the SRC Global Research Collaboration (GRC) program on a project for hardware security. He and his colleagues are designing a fingerprint of microchips with emerging nanoelectronic devices for authentication and encryption. 

The SRC is a global industrial technology research consortium. With its highly regarded university research programs, SRC plays an indispensable part in the R&D strategies of some of industry's most influential entities.Companies who are SRC members include Intel, IBM, Micron, Samsung, ARM, and Taiwan Semiconductor Manufacturing Company, Ltd.

Subscribe to SRC