Khan Chosen for DARPA Young Faculty Award

Dateline

Images

Asif Khan

Asif Khan has been chosen for a DARPA Young Faculty Award. Khan is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he has been on the faculty since 2017.

Khan is receiving this award for his research on ferroelectric field-effect transistors for embedded non-volatile memory applications. Ferroelectric field-effect transistors is one of the most-promising device technologies for artificial intelligence (AI) and machine learning (ML) hardware, due to its energy efficiency and compatibility with high-volume semiconductor manufacturing. The project will focus on solving the critical voltage problem of this device technology, by identifying and implementing new strategies for interface defect reduction in and the downscaling of the ferroelectric gate-dielectric stack. 

Khan works on advanced semiconductor devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for AI/ML/data-centric applications.

His early career work led to the first experimental proof-of-concept demonstration of a physical phenomenon, namely the negative capacitance, in ferroelectric materials, which can reduce the power dissipation in electronic devices below the “fundamental” thermodynamic limit. Negative capacitance is currently a vibrant research area in materials science, condensed matter physics, and electrical engineering, and it is being pursued by all major semiconductor companies for advanced transistor technologies.

In the past, Khan has received multiple awards, including the NSF CAREER Award (2021), the Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). He was also named to the Center for Teaching and Learning Class of 1934 CIOS Honor Roll for his outstanding teaching in ECE8863 Quantum Computing Devices and Hardware in Fall 2020.

Khan’s group currently consists of seven graduate students and two research staff members. They publish in flagship microelectronics conferences, such as the International Electron Devices Meeting (IEDM) and the Symposium on VLSI Technology, and in journals including IEEE Electron Device LettersIEEE Transactions on Electron DevicesNature ElectronicsNature Materials, and Nano Letters. His students received multiple international and Institute-level awards, including the IEEE EDS Masters Student Fellowship (Prasanna Ravindran, 2020) and the Georgia Tech ECE's Colonel Oscar P. Cleaver Award (Nujhat Tasneem in 2018 and Zheng Wang in 2017) for achieving the highest score on the ECE Ph.D. preliminary examination, which was the criteria for the award up to 2018.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

Khan Wins NSF CAREER Award

Dateline

Images

Asif Khan

Asif Khan has been named as a recipient of the NSF CAREER Award. He is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and also holds a courtesy appointment in the School of Materials Science and Engineering.

The title of Khan’s award is “Antiferroelectric Negative Capacitance Transistors for Ultra-low Power Computing,” and it will start on March 15, 2021 and end on February 28, 2026. 

Today's society is experiencing an unprecedented growth of its digital footprint – be it in the form of uploading a photo on Facebook, live-streaming a teaching module to a massive global audience on YouTube, or commandeering a revolution via Twitter. This convenience of modern computing, however, comes with a steep cost in terms of energy use and environmental impact. Today, the global information infrastructure, such as data centers, emit as much greenhouse gases as that of the state of Nevada or a country, such as The Netherlands or Malaysia, and constitute around 1 percent of world-wide electricity demand. According to scientific estimates, this fraction may increase to a double digit percentage in the next 15-20 years. 

At the core of this predicament lies the fact that the fundamental building blocks of digital hardware – the transistors – have long been overdue for a prime upgrade in terms of their energy efficiencies. The proposed research aims to explore an energy-efficient transistor concept – known as a negative capacitance field-effect transistor, using a new class of materials called antiferroelectric oxides. 

Khan joined the ECE faculty in 2017. His research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices, in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/data-centric applications. Khan’s Ph.D. work led to the proof-of-concept demonstration of the negative capacitance phenomenon in ferroelectric materials, which can reduce the power dissipation in electronic devices below the ‘fundamental’ thermodynamic limit. This culminated in the initial development of the field of negative capacitance.

Khan has published 2 book chapters and 70 journal and peer-reviewed conference publications, and he has given 20 invited talks and tutorials at premier microelectronics and ferroelectric conferences. Khan currently has one patent pending at Intel. 

Khan’s awards include the NSF CAREER award (2021), Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). His group at Georgia Tech consists of six Ph.D. students and three research engineers, many of whom won Institute-level and international awards, including an IEEE Electron Devices Society (EDS) Masters Student Fellowship (2020). Khan’s research is supported by the National Science Foundation, the Defense Advanced Research Projects Agency, the Semiconductor Research Corporation, and Intel Corporation. 

Khan has also developed a graduate course, ECE 8863A Quantum Computing Devices and Hardware, as a part of the campus wide response to the national prioritization of quantum computing, known as the National Quantum Initiative Act (NQIA) that was signed by the U.S. president in 2018. Khan recently received the Class of 1934 CIOS Honor Roll award for excellence in teaching this course in Fall 2020. 

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Khan Recognized with 2020 Intel Rising Star Award

Dateline

Asif Khan has been named as one of the 10 awardees of the 2020 Intel Rising Star Award. Khan is an assistant professor at the Georgia Tech School of Electrical and Computer Engineering (ECE).

The purpose of the program is to help promote the careers of early career faculty members who show great promise as future academic leaders in disruptive computing technologies and to foster long term collaborative relationships with Intel. The awards were given based on progressive research in computer science, engineering, and social science in support of the global digital transition in the following areas: software, security, interconnect, memory, architecture, and process.

Khan joined the ECE faculty in 2017, with a courtesy appointment with the School of Materials Science and Engineering. He received his Ph.D. in electrical engineering and computer sciences from the University of California, Berkeley in 2015.

Khan’s research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His group is currently focusing on ferroelectric devices on all aspects ranging from materials physics, growth and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/variable load applications. 

His research group consists of five graduate students and two research staff members. They publish in venues such as the International Electron Devices Meeting, the Symposium on VLSI Technology and CircuitsIEEE Electron Device Letters, IEEE Transactions on Electron Devices, Nature Electronics, Nature Materials, Nano Letters, and Nature.

Khan’s program is supported by the National Science Foundation, the Semiconductor Research Corporation, and the Defense Advanced Research Program Agency. His Ph.D. research led to the first experimental demonstration of the negative capacitance effect in ferroelectrics, which can reduce the energy dissipation in CMOS technology below the fundamental thermodynamic (Boltzmann) limit. One of his publications was cited as one of the nine significant papers in the history of ferroelectricity in a 2020 editorial article in Nature Materials, celebrating the 100th year since the discovery of ferroelectricity in 1920.

Krishna to Have Two Papers Featured in IEEE Micro Top Picks Issue

Dateline

Images

Tushar Krishna will have two of his recent research papers featured in the IEEE Micro“Top Picks from Computer Architecture Conferences,” to be published in the May/June 2019 issue. One paper was selected as an IEEE Micro Top Pick, and another paper was selected as an Honorable Mention. 

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. He has been on the faculty since 2015. 

Every year, IEEE Micro publishes this special issue, which recognizes the year’s top papers that have potential for long-term impact. In order for a paper to be chosen as a top pick, it must first have been accepted in a major computer architecture conference that year. Out of 123 top pick submissions in 2018, 12 were selected as Top Picks and 11 were selected as Honorable Mentions. 

IEEE Micro Top Pick

Krishna’s paper that was selected as a Top Pick is entitled “Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom.” The paper was published at the 45th International Symposium on Computer Architecture (ISCA), held June 2-6, 2018 in Los Angeles, California. Krishna’s coauthors are his recently graduated M.S. student, Aniruddh Ramrakhyani, and Paul Gratz, an ECE associate professor at Texas A&M University.

All high-performance computers today are built by connecting many processors together. These could be cores on a single-chip inside a smartphone or laptop, or servers inside a supercomputer or datacenter. A key challenge in designing the interconnection network connecting these processors is that of “deadlocks”. A deadlock is a scenario where a set of packets is stuck indefinitely and cannot move forward because they form a cyclic dependence. An analogy is that of a traffic jam in road networks where each car waits for the car in front of it to move, but no car can move if they end up forming a cycle. The traditional approaches to avoid deadlocks either restricts routes (leading to lower performance) or adds more queues (leading to more area and power). Unfortunately, paying one of these two expenses is unavoidable today since a deadlock can bring the whole system to a standstill and has to be avoided for functional correctness of any interconnection network.

In this paper, Krishna and his co-authors challenge the theoretical notion of viewing deadlocks as a resource (in this case queues) dependence problem, and view it instead as a lack of coordination between distributed packets. They demonstrate that enabling every packet to move forward at exactly the same time can help them all move forward and get out of the deadlock. Imagine the same traffic jam as before, but every car in the jam agreeing to move forward at exactly the same time to avoid any collisions. This was the first work to show a deadlock-free interconnection network with fully adaptive routing, without any routing restrictions, with only a single queue at every router port.

IEEE Micro Honorable Mention

Krishna’s paper that was selected as an Honorable Mention is entitled “MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.” The paper was published at the 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), held March 24-28, 2018 in Williamsburg, Virginia. Krishna’s coauthors are his Ph.D. students, Hyoukjun Kwon and Ananda Samajdar.

Machine Learning (ML) and Artificial Intelligence (AI) are becoming ubiquitous. Deep Neural Networks (DNN) have demonstrated highly promising results across applications like computer vision, speech recognition, language translation, recommendation systems, and games. The computational complexity of DNNs and a need for high energy-efficiency has led to a surge in research on hardware accelerators. These AI accelerators are designed for keeping the target DNN algorithm in mind, and use custom datapaths and memory hierarchies to provide 10-1000x better performance or energy-efficiency than traditional CPUs and GPUs. Almost every major company today is building its own version of an AI accelerator. However, a key challenge today is that AI/ML algorithms are evolving at an extremely rapid rate - almost daily, while designing and taping out a hardware chip takes millions of dollars, and replacing these chips every time the algorithm changes is not practical. Thus, an open question today is how to design an accelerator chip that can be built and deployed (on smartphones and/or datacenters) and will be able to run both current and future algorithms efficiently, without having to be replaced frequently.

In their paper, Krishna and his students address this issue by adding lightweight, non-blocking, and reconfigurable interconnects within a DNN accelerator called MAERI. They demonstrate that almost any DNN model can be mapped while utilizing close to 100 percent of the accelerator’s compute resources, by simply reconfiguring the proposed interconnects appropriately. This makes the MAERI approach future-proof to innovations across DNN models and dataflow/mapping techniques.

Krishna Tapped for Google Faculty Research Award

Dateline

Images

Tushar Krishna has been named as one of the recipients of the Google Faculty Research Award (FRA). Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE).

The Google FRA program focuses on funding world-class technical research in Computer Science, Engineering, and related fields. Among 910 proposals from 40 countries and over 320 universities submitted this year, 158 projects were selected for funding. The goal of the Google FRA is to identify and strengthen long-term collaborative relationships with faculty working on problems that will impact how future generations use technology. The award is highly competitive – only 15 percent of applicants receive funding – and each proposal goes through a rigorous Google-wide review process.

The title of Krishna’s award-winning proposal was "Using ML to Design ML Accelerators." With the end of Moore’s Law, the performance of conventional CPUs has stagnated. The growing computing demands from applications, such as Machine Learning (ML), has led to an explosion of custom hardware accelerators (across several companies and startups) for running Machine Learning algorithms at real-time latency and high energy-efficiency. 

A key challenge, however, is that the design space of these accelerators is extremely huge due to an increasing and rapidly evolving suite of Artificial Intelligence/ML models, different requirements for training vs. inference, a plethora of dataflow approaches for minimizing data movement, and varying area-power budgets depending on the target device. Krishna’s proposal seeks to enable rapid design and deployment of ML accelerators by leveraging ML algorithms to efficiently represent and search through this hardware design space.

An ECE faculty member since 2015, Krishna leads the Synergy Lab at Georgia Tech. He and his team focus on architecting next-generation intelligent computer systems and interconnection networks for emerging application areas such as machine learning. Krishna also received an NSF CISE Research Initiation Initiative Award in 2018. He recently had one of his papers selected as an IEEE Micro Top Pick from computer architecture conferences and a second paper was selected as an Honorable Mention; Krishna’s work will be acknowledged in the May/June 2019 issue of IEEE Micro.

Krishna Chosen for Facebook Research Faculty Award

Dateline

Images

Tushar Krishna has been chosen as one of the recipients of Facebook Research's Faculty Award for AI System Hardware/Software Co-Design. Krishna was among the eight winners who were selected from 88 worldwide submissions.  

The title of Krishna’s award-winning project is “ML-Driven HW-SW Co-Design of Efficient Tensor Core Architectures.” In this project, co-design implies simultaneous design and optimization of several aspects of the system, including hardware and software, to achieve a set target for a given system metric, such as throughput, latency, power, size, or any combination these factors. 

Artificial intelligence (AI) and deep learning have been particularly amenable to such co-design processes across various parts of the software and hardware stack, leading to a variety of novel algorithms, numerical optimizations, and AI hardware. Krishna’s proposal focuses on creating an automated machine learning (ML)-driven closed-loop system to generate custom AI hardware platforms for the target algorithms and/or performance/energy constraints using a library of lego-like heterogeneous hardware building blocks.

Krishna has been an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. He and his team focus on architecting next-generation intelligent computer systems and interconnection networks for emerging application areas such as machine learning. Krishna has received a Google Faculty Research Award and an NSF CISE Research Initiation Initiative Award. He recently had one of his papers selected as an IEEE Micro Top Pick from computer architecture conferences and a second paper was selected as an Honorable Mention; Krishna’s work will be acknowledged in the May/June 2019 issue of IEEE Micro.

Yu to Receive Inaugural SRC Young Faculty Award

Dateline

Keywords

SRC

Images

Shimeng Yu

Shimeng Yu has been named as the recipient of the inaugural Semiconductor Research Corporation (SRC) Young Faculty Award. 

An associate professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), Yu will be presented with the award at the annual SRC TECHCON meeting, to be held September 9-10, 2019 in Austin, Texas. He is also a member of the Institute for Electronics and Nanotechnology. This new award is presented to an untenured full-time faculty member who is a principal investigator (PI) or co-principal investigator working on research that greatly enriches the SRC research agenda.

Yu has been a member of Tech’s ECE faculty since August 2018, where he leads the Laboratory for Emerging Devices and Circuits. Yu is involved in several SRC projects. 

  • Yu is a member of the Applications and Systems-Driven Center for Energy-Efficient Integrated NanoTechnologies (ASCENT), which is part of the SRC/DARPA Joint University Microelectronics Program. ASCENT's mission is to provide breakthrough advances in integrated nanoelectronics to sustain the promise of Moore’s Law. Led by the University of Notre Dame, along with 13 partner universities and 29 principal investigators, the Center is funded for $49 million over five years. Yu's specific research within ASCENT develops emerging nanoelectronic devices that emulate the synapses and neurons to build hardware platforms for machine learning and neuromorphic computing. 
  • He is a member of the SRC nanoelectronic COmputing REsearch (nCORE) program, in particular the Energy-Efficient Computing: From Devices to Architectures (E2CDA) program. In this effort, jointly funded with the National Science Foundation, Yu is developing a software simulation framework to benchmark the emerging device technology's impact on artificial intelligence across the layers from algorithms, computer architecture, and circuit and chip design down to devices and materials. 
  • Yu is a PI of the SRC Global Research Collaboration (GRC) program on a project for hardware security. He and his colleagues are designing a fingerprint of microchips with emerging nanoelectronic devices for authentication and encryption. 

The SRC is a global industrial technology research consortium. With its highly regarded university research programs, SRC plays an indispensable part in the R&D strategies of some of industry's most influential entities.Companies who are SRC members include Intel, IBM, Micron, Samsung, ARM, and Taiwan Semiconductor Manufacturing Company, Ltd.

Krishna Wins Facebook Research Faculty Award for Second Straight Year

Dateline

Images

Tushar Krishna has been chosen as one of the recipients of the Facebook Research Faculty Award for AI System Hardware/Software Co-Design. Krishna was among the nine winners who were selected from 132 worldwide submissions. This is the second year in a row that Krishna has won this award.

The title of Krishna’s award-winning project is “HW/SW co-design of next-generation training platforms for DLRMs.” DLRMs stand for Deep Learning Recommendation Models and are used within online recommendation systems, such as ranking of search queries in Google, friend suggestions on Facebook, and job advertisements from LinkedIn. DLRMs are very different from Deep Learning models used for computer vision and natural language processing as they involve both continuous (or dense) features and categorical (or sparse) features. For example, the date and time for clicks on a webpage by a user can be used as dense features, while the representation of the user based on all the webpages visited by him/her in the past 48 hours can be used as sparse features for training recommendation models. The dense features are processed with multilayer perceptrons (MLPs) while the sparse features are processed using a technique called embeddings.

Training DLRMs constitutes more than 50 percent of the training demand in companies like Facebook. This is because storing the embeddings requires significant memory capacity, on the order of 100s of gigabytes to a few terabytes, which is more than the memory available on a single accelerator (GPU or TPU) node. Thus, DLRMs require clever partitioning and distribution of the model across multiple accelerator nodes. This naturally makes it crucial to optimize the communication between these nodes to reduce overall training time.

As part of the award, Krishna will explore mechanisms for efficient distributed training of recommendations models. The research will develop techniques involving co-design across software and hardware to enable scalability across 100s-1000s of accelerator nodes. The research effort will leverage ASTRA-sim, a distributed DL training simulator developed by Krishna and his Ph.D. student Saeed Rashidi in collaboration with Facebook and Intel.

Krishna is an assistant professor in the School of Electrical and Computer Engineering at Georgia Tech. He also holds the ON Semiconductor Junior Professorship. Krishna has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E. in Electrical Engineering from Princeton University (2009), and a B.Tech. in Electrical Engineering from the Indian Institute of Technology, Delhi (2007). Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and three have won best paper awards. He received the National Science Foundation CRII award in 2018 and both a Google Faculty Award and a Facebook Faculty Award in 2019.

Artificial Intelligence Course Creates AI Teaching Assistant

Subtitle

Students didn’t know their TA was a computer

Dateline

Images

Ashok Goel is a professor in the School of Interactive Computing.

College of Computing Professor Ashok Goel teaches Knowledge Based Artificial Intelligence (KBAI) every semester. It’s a core requirement of Georgia Tech’s online master’s of science in computer science program. And every time he offers it, Goel estimates, his 300 or so students post roughly 10,000 messages in the online forums — far too many inquiries for him and his eight teaching assistants (TA) to handle.

That’s why Goel added a ninth TA this semester. Her name is Jill Watson, and she’s unlike any other TA in the world. In fact, she’s not even a “she.” Jill is a computer — a virtual TA — implemented, in part, using technologies from IBM’s Watson platform.

“The world is full of online classes, and they’re plagued with low retention rates,” Goel said. “One of the main reasons many students drop out is because they don’t receive enough teaching support. We created Jill as a way to provide faster answers and feedback.”

Goel and his team of Georgia Tech graduate students started to build her last year. They contacted Piazza, the course’s online discussion forum, to track down all the questions that had ever been asked in KBAI since the class was launched in fall 2014 (about 40,000 postings in all). Then they started to feed Jill the questions and answers.

“One of the secrets of online classes is that the number of questions increases if you have more students, but the number of different questions doesn’t really go up,” Goel said. “Students tend to ask the same questions over and over again.”

That’s an ideal situation to apply computing technologies like Watson. Goel tapped into IBM's open developer platform to identify Watson APIs for answering questions, adding Georgia Tech’s own processing modules to improve performance. The team then wrote code that allows Jill to field routine questions that are asked every semester. For example, students consistently ask where they can find particular assignments and readings.

Jill wasn’t very good for the first few weeks after she started in January, often giving odd and irrelevant answers. Her responses were posted in a forum that wasn’t visible to students.

“Initially her answers weren't good enough because she would get stuck on keywords,” said Lalith Polepeddi, one of the graduate students who co-developed the virtual TA. “For example, a student asked about organizing a meet-up to go over video lessons with others, and Jill gave an answer referencing a textbook that could supplement the video lessons — same keywords — but different context. So we learned from mistakes like this one, and gradually made Jill smarter.”

After some tinkering by the research team, Jill found her groove and soon was answering questions with 97 percent certainty. When she did, the human TAs would upload her responses to the students. By the end of March, Jill didn’t need any assistance: She wrote the class directly if she was 97 percent positive her answer was correct.

The students, who were studying artificial intelligence, were unknowingly interacting with it. Goel didn’t inform them about Jill's true identity until April 26. The student response was uniformly positive. One admitted her mind was blown. Another asked if Jill could “come out and play.” Since then some students have organized a KBAI alumni forum to learn about new developments with Jill after the class ends, and another group of students has launched an open source project to replicate her.

Back in February, student Tyson Bailey began to wonder if Jill was a computer and posted his suspicions on Piazza.

“We were taking an AI course, so I had to imagine that it was possible there might be an AI lurking around,” said Bailey, who lives in Albuquerque, New Mexico. “Then again, I asked Dr. Goel if he was a computer in one of my first email interactions with him. I think it’s a great idea and hope that they continue to improve it.”

Jill ended the semester able to answer many routine questions asked. She’ll return —with a different name — next semester. The goal is to have the virtual teaching assistant answer 40 percent of all questions by the end of year.

Location

Atlanta, GA

Email

maderer@gatech.edu

Contact

Jason Maderer
National Media Relations
maderer@gatech.edu
404-660-2926

Subscribe to artificial intelligence