Khan Wins NSF CAREER Award

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Asif Khan

Asif Khan has been named as a recipient of the NSF CAREER Award. He is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and also holds a courtesy appointment in the School of Materials Science and Engineering.

The title of Khan’s award is “Antiferroelectric Negative Capacitance Transistors for Ultra-low Power Computing,” and it will start on March 15, 2021 and end on February 28, 2026. 

Today's society is experiencing an unprecedented growth of its digital footprint – be it in the form of uploading a photo on Facebook, live-streaming a teaching module to a massive global audience on YouTube, or commandeering a revolution via Twitter. This convenience of modern computing, however, comes with a steep cost in terms of energy use and environmental impact. Today, the global information infrastructure, such as data centers, emit as much greenhouse gases as that of the state of Nevada or a country, such as The Netherlands or Malaysia, and constitute around 1 percent of world-wide electricity demand. According to scientific estimates, this fraction may increase to a double digit percentage in the next 15-20 years. 

At the core of this predicament lies the fact that the fundamental building blocks of digital hardware – the transistors – have long been overdue for a prime upgrade in terms of their energy efficiencies. The proposed research aims to explore an energy-efficient transistor concept – known as a negative capacitance field-effect transistor, using a new class of materials called antiferroelectric oxides. 

Khan joined the ECE faculty in 2017. His research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices, in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/data-centric applications. Khan’s Ph.D. work led to the proof-of-concept demonstration of the negative capacitance phenomenon in ferroelectric materials, which can reduce the power dissipation in electronic devices below the ‘fundamental’ thermodynamic limit. This culminated in the initial development of the field of negative capacitance.

Khan has published 2 book chapters and 70 journal and peer-reviewed conference publications, and he has given 20 invited talks and tutorials at premier microelectronics and ferroelectric conferences. Khan currently has one patent pending at Intel. 

Khan’s awards include the NSF CAREER award (2021), Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). His group at Georgia Tech consists of six Ph.D. students and three research engineers, many of whom won Institute-level and international awards, including an IEEE Electron Devices Society (EDS) Masters Student Fellowship (2020). Khan’s research is supported by the National Science Foundation, the Defense Advanced Research Projects Agency, the Semiconductor Research Corporation, and Intel Corporation. 

Khan has also developed a graduate course, ECE 8863A Quantum Computing Devices and Hardware, as a part of the campus wide response to the national prioritization of quantum computing, known as the National Quantum Initiative Act (NQIA) that was signed by the U.S. president in 2018. Khan recently received the Class of 1934 CIOS Honor Roll award for excellence in teaching this course in Fall 2020. 

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Khan Recognized with 2020 Intel Rising Star Award

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Asif Khan has been named as one of the 10 awardees of the 2020 Intel Rising Star Award. Khan is an assistant professor at the Georgia Tech School of Electrical and Computer Engineering (ECE).

The purpose of the program is to help promote the careers of early career faculty members who show great promise as future academic leaders in disruptive computing technologies and to foster long term collaborative relationships with Intel. The awards were given based on progressive research in computer science, engineering, and social science in support of the global digital transition in the following areas: software, security, interconnect, memory, architecture, and process.

Khan joined the ECE faculty in 2017, with a courtesy appointment with the School of Materials Science and Engineering. He received his Ph.D. in electrical engineering and computer sciences from the University of California, Berkeley in 2015.

Khan’s research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His group is currently focusing on ferroelectric devices on all aspects ranging from materials physics, growth and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/variable load applications. 

His research group consists of five graduate students and two research staff members. They publish in venues such as the International Electron Devices Meeting, the Symposium on VLSI Technology and CircuitsIEEE Electron Device Letters, IEEE Transactions on Electron Devices, Nature Electronics, Nature Materials, Nano Letters, and Nature.

Khan’s program is supported by the National Science Foundation, the Semiconductor Research Corporation, and the Defense Advanced Research Program Agency. His Ph.D. research led to the first experimental demonstration of the negative capacitance effect in ferroelectrics, which can reduce the energy dissipation in CMOS technology below the fundamental thermodynamic (Boltzmann) limit. One of his publications was cited as one of the nine significant papers in the history of ferroelectricity in a 2020 editorial article in Nature Materials, celebrating the 100th year since the discovery of ferroelectricity in 1920.

Zajic Appointed as a Ken Byers Professor

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Alenka Zajic has been appointed as a Ken Byers Professor, effective October 1, 2020. Zajic is a member of the faculty at the Georgia Tech School of Electrical and Computer Engineering (ECE), where she currently holds the rank of associate professor.  

After graduating from Georgia Tech with her Ph.D. in 2008, Zajic spent a year as a postdoctoral fellow at the Naval Research Laboratory and two years as a visiting assistant professor in Tech's School of Computer Science. In 2012, she joined ECE as an assistant professor, and in 2017, she was promoted to associate professor. 

Zajic leads the Electromagnetic Measurements in Communications and Computing Laboratory, where she advises 10 Ph.D. students and two postdoctoral fellows who work in the areas of propagation, enabling communication, and improving data security in challenging environments, such as vehicle-to-vehicle wireless radio communications, underwater acoustic communications, and communications inside a processor chip. To date, Zajic has graduated nine Ph.D. students and five M.S. students. She advises undergraduate students on individual projects and through the Opportunity Research Scholars Program. Zajic and her research group have received six best paper, poster, or demonstration awards since she joined ECE as a faculty member.

Zajic’s specific research interests focus on understanding mechanisms that generate electromagnetic (EM) side-channel emanations in modern computers and on locating sources of information-carrying EM emanations in complex environments. She has received over $18 million in research funding as a PI or co-PI, mostly from NSF, DARPA, the Office of Naval Research, and the Air Force Office of Scientific Research. Zajic has published over 140 refereed journal and conference publications. She has three awarded patents and five patent applications pending. Her work has been publicized locally and internationally through The Atlanta Journal-Constitution, NSF Science 360, Voice of America, Wired, and many other outlets. Zajic has served as an editor of the IEEE Transactions on Wireless Communications and Wiley Transactions on Emerging Telecommunications Technologies. She also served as the chair of the Atlanta chapter of the IEEE Microwave Theory and Techniques Society/Antennas and Propagation Society from 2015-2017, and during that time, the group received the IEEE Outstanding Chapter Award in 2016. She received the IEEE Atlanta Section Outstanding Engineer Award in 2019. 

Equally devoted to teaching excellence and service, Zajic has developed or redesigned both undergraduate and graduate courses and has taught a flipped classroom version of ECE 3025–Electromagnetics. For her efforts, she has received several teaching awards, including the Richard M. Bass/Eta Kappa Nu Outstanding Junior Teacher Award in 2016 and the LexisNexis Dean’s Excellence Award in 2016-2017. Zajic has also participated in the Center for Teaching and Learning’s Class of 1969 Teaching Scholars Program. She is an active member of the ECE and Georgia Tech community, currently serving as the director of the M.S. Cybersecurity degree program; a member of the ECE Statutory Advisory Committee; a member of the College of Engineering Reappointment, Promotion, and Tenure committee; and a member of a working group on the professional development of graduate students, an initiative coordinated from the Provost’s Office.

Saltaformaggio Wins ACM SIGSAC Doctoral Dissertation Award

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Brendan Saltaformaggio

Brendan Saltaformaggio received the 2017 ACM SIGSAC Doctoral Dissertation Award at the ACM Conference on Computer and Communications Security (ACM CCS), which was held October 30-November 3 in Dallas, Texas. SIGSAC is the Special Interest Group on Security, Audit, and Control in the Association for Computing Machinery (ACM).

An assistant professor at the Georgia Tech School of Electrical and Computer Engineering (ECE), Saltaformaggio was recognized for his Ph.D. dissertation, “Convicted by Memory: Automatically Recovering Spatial-Temporal Evidence from Memory Images.” He received his Ph.D. in Computer Science from Purdue University in 2016.

Saltaformaggio’s dissertation pioneered new cyber forensic techniques that help investigators solve crimes. Much of his work focused on memory image forensics, a key area in cyber forensics that involves recovering digital evidence from memory (RAM) images captured from the criminal or victim's device such as a PC or smartphone.

Saltaformaggio’s dissertation challenged the state-of-the-art of memory forensics by breaking away from brute force data-carving approaches. Instead, his research developed a series of binary-analysis-driven techniques that automatically reconstruct and render in-memory forensic evidence, even if a suspect has locked or encrypted their device.

A member of the ECE faculty since this past July, Saltaformaggio leads the Cyber Forensics Innovation (CyFI) Laboratory. The CyFI Lab's mission is to further the investigation of advanced cyber crimes and the analysis and prevention of next-generation malware attacks, particularly in mobile and IoT environments. He is also a member of Georgia Tech’s Institute for Information Security & Privacy.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Stüber Selected for IEEE Communications Society RCC Award

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Gordon Stüber

Gordon L. Stüber has been named the recipient of the 2017 IEEE Communications Society Radio Communications Committee (RCC) Technical Recognition Award. The award will be presented at the next RCC meeting, which will be held during IEEE GLOBECOM 2017 on December 4-8 in Singapore.

The RCC Technical Recognition Award aims to promote radio communications research and development activities in both academia and industry. 

Stüber has been on the Georgia Tech School of Electrical and Computer Engineering (ECE) faculty since 1986 and currently holds the Joseph M. Pettit Chair Professorship. He leads the research of the Wireless Systems Laboratory, which focuses on physical layer wireless communications and communication signal processing.

Stüber has published over 300 refereed journal and conference papers in these areas and has graduated 32 Ph.D. students. He is also the author of the textbook, Principles of Wireless Communications, 4/e, 2017. Stüber has served as an elected Member-at-Large on the IEEE Communication Society Board of Governors, and is currently an elected Member of the IEEE Vehicular Technology Society Board of Governors, where he serves as the Awards Committee Chair. 

Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) partners with Notre Dame in $26 million multi-university research center developing next-generation computing technologies

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John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.
Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology

In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.

With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).

Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) led by Profs. A. Raychowdhury and M. Swaminathan, deputy director and director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.

The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.

Profs. Raychowdhury (PI) and Swaminathan (co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.

“Our involvement in the ASCENT center provides us with unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof. Raychowdhury, the ON Semiconductor Jr. Associate Professor of VLSI Systems.

“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”

This is one of the largest JUMP centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies.  Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.

- Christa M. Ernst

Krishna Selected for NSF CRII Award

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Tushar Krishna has been selected for a National Science Foundation (NSF) CISE Research Initiation Initiative Award.

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. This two-year-long NSF award will support his project entitled “Enabling Neuroevolution in Hardware.”

Over the past few years, machine learning algorithms, especially neural networks (NN) have seen a surge of popularity owing to their potential in solving a wide variety of complex problems across image classification and speech recognition. Unfortunately, in order to be effective, NNs need to have the appropriate topology (connections between neurons) for the task at hand and have the right weights on the connections. This is known as supervised learning and requires training the NN by running it through terabytes to petabytes of data.

This form of machine learning is infeasible for the emerging domain of autonomous systems (robots/drones/cars) which will often operate in environments where the right topology for the task may be unknown or is constantly changing, and robust training data is not available. Autonomous systems need the ability to mirror human-like learning, where we are continuously learning, and often from experiences rather than being explicitly trained. This is known as reinforcement learning.



The focus of Krishna’s research will be on neuroevolution (NE), a class of reinforcement learning algorithms that evolve NN topologies and weights for the task at hand using evolutionary algorithms. The goal of this project will be on enabling NE in energy-constrained autonomous devices by leveraging opportunities for parallelism and hardware acceleration. If successful, this research could enable mass proliferation of autonomous drones and robots that can learn to perform tasks without being explicitly trained.

EDA’s CAEML Grows More Humps: Al Expands Role in Design

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John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.

The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.

Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.

“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”

Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.

After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.

Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."

Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).

“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”

https://www.eetimes.com/document.asp?doc_id=1332917

Li Honored with IEEE Best Paper Award

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Geoffrey Ye Li has been named the recipient of the 2017 IEEE Donald G. Fink Overview Paper Award, which is given by the IEEE Signal Processing Society.

This award recognizes a journal article that has had substantial impact over several years on a subject related to the Society’s technical scope. Li will be presented with this award at the 2018 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), to be held April 15-20 in Calgary, Alberta, Canada.

The title of the award-winning paper is “An Overview of Massive MIMO: Benefits and Challenges,” published in the IEEE Journal of Selected Topics in Signal Processing, volume 8, number 5 in October 2014. Massive MIMO wireless communications have attracted much attention for their potential to tremendously improve spectral and energy efficiency of networks using relatively simple processing. Techniques related to massive MIMO have been extensively investigated. As one of the first comprehensive surveys on massive MIMO, this overview article has served as an excellent reference and a starting point for readers interested in massive MIMO topics in the past several years. 

Li is a professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and has been on the faculty since 2000. His coauthors are Lu Lu, a Ph.D. graduate of Li’s research group–the Information Transmission and Processing Laboratory–and who now works with Intel in Portland, Oregon; A. Lee Swindlehurst, a professor in the Henry Samueli School of Engineering at the University of California, Irvine; Alexei Ashikhmin, distinguished member of the technical staff of Bell Labs in New Jersey; and Rui Zhang, an associate professor in the Department of ECE at the National University of Singapore.

Saltaformaggio Tapped for NSF CRII Award

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Brendan Saltaformaggio

Brendan D. Saltaformaggio has received the CISE Research Initiation Initiative (CRII) Award from the National Science Foundation (NSF).

Saltaformaggio is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Cyber Forensics Innovation Laboratory. The title of his research project is "GEMINI: Guided Execution Based Mobile Advanced Persistent Threat Investigation.” 

Advanced persistent threat (APT) campaigns are increasingly targeting mobile devices deployed across corporations, governments, and financial institutions. Unfortunately, prohibitively slow responses to even high-profile APT attacks have shown that authorities lack the capability to quickly investigate ongoing attacks (in a matter of hours or days rather than months). To address this challenge, Saltaformaggio’s research draws inspiration from recent developments in memory image forensics, in particular a recently introduced technique called guided execution. This technique has provided rapid evidence collection and crime investigation capabilities currently unparalleled in APT investigation.

Through this research, Saltaformaggio is developing an integrated framework, called GEMINI, which shifts the goal of modern memory forensics from the investigation of physical-world crimes to APT campaigns. Based on the analysis of only a single memory image – collected from an Android device after an attack is suspected – GEMINI provides the following set of APT investigation capabilities:

  • Based on exploratory guided execution techniques, GEMINI can search for and re-create previously enacted APT attack stages.
  • Beyond investigating prior attack execution, GEMINI enables the revelation of hidden/potential future attack behaviors by “puppeteering” their executing with pre-staged memory image data.
  • After exploring future payloads, GEMINI can further leverage its guided execution capabilities for the remediation of the observed attack strategies.

This work directly contributes to national security by advancing research in and developing techniques for the investigation of APT campaigns targeting mobile devices. In addition, the results of this research are being made publicly available with the goal of enhancing discovery and empowering future research in this area, as well as contributing to the development of new curriculum materials focused on malware analysis and reverse engineering.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

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