Khan Chosen for DARPA Young Faculty Award



Asif Khan

Asif Khan has been chosen for a DARPA Young Faculty Award. Khan is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he has been on the faculty since 2017.

Khan is receiving this award for his research on ferroelectric field-effect transistors for embedded non-volatile memory applications. Ferroelectric field-effect transistors is one of the most-promising device technologies for artificial intelligence (AI) and machine learning (ML) hardware, due to its energy efficiency and compatibility with high-volume semiconductor manufacturing. The project will focus on solving the critical voltage problem of this device technology, by identifying and implementing new strategies for interface defect reduction in and the downscaling of the ferroelectric gate-dielectric stack. 

Khan works on advanced semiconductor devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for AI/ML/data-centric applications.

His early career work led to the first experimental proof-of-concept demonstration of a physical phenomenon, namely the negative capacitance, in ferroelectric materials, which can reduce the power dissipation in electronic devices below the “fundamental” thermodynamic limit. Negative capacitance is currently a vibrant research area in materials science, condensed matter physics, and electrical engineering, and it is being pursued by all major semiconductor companies for advanced transistor technologies.

In the past, Khan has received multiple awards, including the NSF CAREER Award (2021), the Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). He was also named to the Center for Teaching and Learning Class of 1934 CIOS Honor Roll for his outstanding teaching in ECE8863 Quantum Computing Devices and Hardware in Fall 2020.

Khan’s group currently consists of seven graduate students and two research staff members. They publish in flagship microelectronics conferences, such as the International Electron Devices Meeting (IEDM) and the Symposium on VLSI Technology, and in journals including IEEE Electron Device LettersIEEE Transactions on Electron DevicesNature ElectronicsNature Materials, and Nano Letters. His students received multiple international and Institute-level awards, including the IEEE EDS Masters Student Fellowship (Prasanna Ravindran, 2020) and the Georgia Tech ECE's Colonel Oscar P. Cleaver Award (Nujhat Tasneem in 2018 and Zheng Wang in 2017) for achieving the highest score on the ECE Ph.D. preliminary examination, which was the criteria for the award up to 2018.


Atlanta, GA



Jackie Nemeth

School of Electrical and Computer Engineering

Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) partners with Notre Dame in $26 million multi-university research center developing next-generation computing technologies



John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.
Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology

In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.

With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).

Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) led by Profs. A. Raychowdhury and M. Swaminathan, deputy director and director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.

The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.

Profs. Raychowdhury (PI) and Swaminathan (co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.

“Our involvement in the ASCENT center provides us with unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof. Raychowdhury, the ON Semiconductor Jr. Associate Professor of VLSI Systems.

“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”

This is one of the largest JUMP centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies.  Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.

- Christa M. Ernst

EDA’s CAEML Grows More Humps: Al Expands Role in Design



John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.

The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.

Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.

“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”

Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.

After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.

Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."

Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).

“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”

Wang Tapped for DARPA Young Faculty Award



Hua Wang has received a DARPA Young Faculty Award (YFA) for his research on mm-Wave power amplifiers with extreme bandwidth and energy efficiency.

A member of the Georgia Tech School of Electrical and Computer Engineering faculty since 2012, Wang holds the Demetrius T. Paris Junior Professorship and leads the Georgia Tech Electronics and Micro-System (GEMS) Lab. He has also received multiple prestigious academic awards, including the IEEE MTT-S Outstanding Young Engineer Award in 2017, Georgia Tech Sigma Xi Young Faculty Award in 2016, National Science Foundation (NSF) CAREER Award in 2015, Roger P. Webb ECE Outstanding Junior Faculty Member Award in 2015, and Lockheed Dean’s Excellence in Teaching Award in 2015, as well as many best paper awards in the field of solid-state circuits, systems, and microwave engineering. Wang is also a Distinguished Lecturer for the IEEE Solid-State Circuits Society for 2018 and 2019.

As millimeter-wave frequency applications have become prevalent in the commercial and Department of Defense markets, there is a rapidly growing need for advanced millimeter-wave solid-state power amplifier technologies that can support high energy efficiency, sufficient output power, and high-speed complex modulations. Moreover, high-efficiency amplifiers covering extremely wide bandwidth have become a necessity, particularly for frequency-agile massive Multiple-Input-Multiple-Output (MIMO) systems, such as multi-standard 5G wireless communication.

In this project, Wang will lead the fundamental research on a completely new class of extremely-wideband-yet-efficient power amplifiers over the frequency range of 30-100GHz. The key technology innovations include novel amplifier circuit topologies, hybrid use of silicon/non-silicon solid-state devices, and multi-mode amplifier operations.

This project will potentially achieve a new class of load modulation power amplifiers with an unprecedented combination of bandwidth, energy efficiency, and output power. Such amplifier technologies will eventually enable true “common-module front-ends” for reconfigurable transmitters and MIMO systems with "full-spectrum access" and digital beam-forming for wireless communication, radar, imaging, and spectrum sensing applications.

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