Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) partners with Notre Dame in $26 million multi-university research center developing next-generation computing technologies

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John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.
Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology

In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.

With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).

Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) led by Profs. A. Raychowdhury and M. Swaminathan, deputy director and director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.

The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.

Profs. Raychowdhury (PI) and Swaminathan (co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.

“Our involvement in the ASCENT center provides us with unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof. Raychowdhury, the ON Semiconductor Jr. Associate Professor of VLSI Systems.

“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”

This is one of the largest JUMP centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies.  Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.

- Christa M. Ernst

EDA’s CAEML Grows More Humps: Al Expands Role in Design

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John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.

The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.

Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.

“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”

Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.

After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.

Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."

Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).

“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”

https://www.eetimes.com/document.asp?doc_id=1332917

Spring 2018 IEN Seed Grant Winners Announced

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Fall 2017 Seed Grant Winner at the IEN User Poster Session on May 21, 2018 - Arith Rajapaks

The Institute for Electronics and Nanotechnology at Georgia Tech has announced the winners for the 2018 Spring Seed Grant Awards. The primary purpose of the IEN Seed Grant is to give first or second year graduate students in various disciplines working on original and un-funded research in micro- and nano-scale projects the opportunity to access the most advanced academic cleanroom space in the Southeast. In addition to accessing the high-level fabrication, lithography, and characterization tools in the labs, the students will have the opportunity to gain proficiency in cleanroom and tool methodology and to use the consultation services provided by research staff members of the IEN Advanced Technology Team.  In addition, the Seed Grant program gives faculty with novel research topics the ability to develop preliminary data in order to pursue follow-up funding sources.

Over the course of five years, this grant program has seeded forty-five projects with forty-nine students working in ten different schools in COE and COS, as well as the Georgia Tech Research Institute and 2 external projects.

The 4 winning projects, from a diverse group of engineering disciplines, were awarded a six-month block of IEN cleanroom and lab access time. In keeping with the interdisciplinary mission of IEN, the projects that will be enabled by the grants include research in materials, biomedicine, energy production, and microelectronics packaging applications.

The Spring 2018 IEN Seed Grant Award winners are:

  • Jiang Chen (PI Ben Wang - MSE): Validation and Characterization of Living Cell Grafting on Polycaprolactone Fibers for Textile Tissue Engineering
  • Fatima Chrit (PI Alexander Alexeev - ME): Microfluidic Adhesion-based Sorting of Biological Cells
  • Zifei Sun (PI Gleb Yushin - MSE): FeOx Coated FeF3-C Nanofibers as Free-standing Cathodes for Sodium- Ion Batteries
  • Ting Wang (PI Xing Xie - Civil and Environmental Engineering): Development of Lab-on-a-Chip Devices for the Mechanisms Study of Cell Transportation and Bacteria Inactivation in a Non-Uniform Electric Field

Awardees will present the results of their research efforts at the annual IEN User Day in 2019.

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