Krishna Selected for NSF CRII Award

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Tushar Krishna has been selected for a National Science Foundation (NSF) CISE Research Initiation Initiative Award.

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. This two-year-long NSF award will support his project entitled “Enabling Neuroevolution in Hardware.”

Over the past few years, machine learning algorithms, especially neural networks (NN) have seen a surge of popularity owing to their potential in solving a wide variety of complex problems across image classification and speech recognition. Unfortunately, in order to be effective, NNs need to have the appropriate topology (connections between neurons) for the task at hand and have the right weights on the connections. This is known as supervised learning and requires training the NN by running it through terabytes to petabytes of data.

This form of machine learning is infeasible for the emerging domain of autonomous systems (robots/drones/cars) which will often operate in environments where the right topology for the task may be unknown or is constantly changing, and robust training data is not available. Autonomous systems need the ability to mirror human-like learning, where we are continuously learning, and often from experiences rather than being explicitly trained. This is known as reinforcement learning.



The focus of Krishna’s research will be on neuroevolution (NE), a class of reinforcement learning algorithms that evolve NN topologies and weights for the task at hand using evolutionary algorithms. The goal of this project will be on enabling NE in energy-constrained autonomous devices by leveraging opportunities for parallelism and hardware acceleration. If successful, this research could enable mass proliferation of autonomous drones and robots that can learn to perform tasks without being explicitly trained.

Five ECE Faculty Members Honored with CTL Award

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Lukas Graber
Benjamin Yan

John D. Cressler, Lukas Graber, Tushar Krishna, Sung Kyu Lim, and Benjamin Yang have been chosen for the Georgia Tech Center for Teaching and Learning (CTL) Class of 1940 Course Survey Teaching Effectiveness Award. They will be formally recognized in March 2019 when CTL holds its annual Celebrating Teaching Day.

This Class of 1940 distinction is one of several awards made annually by CTL to instructors of small and large classes. The award recognizes faculty members with exceptional response rates and scores on the Course-Instructor Opinion Surveys (CIOS). A high response rate (85 percent or greater) and a near-perfect evaluation score were also required for consideration. 

Cressler is being recognized for his outstanding teaching in IAC 2002 Science, Engineering, and Religion: An Interfaith Dialogue. He holds the Schlumberger Chair Professorship in Electronics in the School of Electrical and Computer Engineering (ECE) and leads the Silicon-Germanium Devices and Circuits Group.

Graber is being honored for his outstanding teaching in ECE 4012 ECE Culminating Design Project II. He is an assistant professor in ECE and leads the Plasma and Dielectrics Laboratory.

Krishna is being recognized for his outstanding teaching in ECE 8823 Interconnection Networks for High-Performance Systems. He is an assistant professor in ECE and leads the Synergy Lab.

Lim is being honored for his outstanding teaching in ECE 2020 Fundamentals of Digital System Design. He holds the Dan Fielder Professorship and leads the Georgia Tech Computer-Aided Design Lab.

Yang is being recognized for his outstanding teaching in ECE 2026 Introduction to Signal Processing. A frequent instructor of ECE courses, Yang is a senior research engineer in the Georgia Tech Research Institute’s Electro-Optical Systems Laboratory.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Krishna to Have Two Papers Featured in IEEE Micro Top Picks Issue

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Tushar Krishna will have two of his recent research papers featured in the IEEE Micro“Top Picks from Computer Architecture Conferences,” to be published in the May/June 2019 issue. One paper was selected as an IEEE Micro Top Pick, and another paper was selected as an Honorable Mention. 

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. He has been on the faculty since 2015. 

Every year, IEEE Micro publishes this special issue, which recognizes the year’s top papers that have potential for long-term impact. In order for a paper to be chosen as a top pick, it must first have been accepted in a major computer architecture conference that year. Out of 123 top pick submissions in 2018, 12 were selected as Top Picks and 11 were selected as Honorable Mentions. 

IEEE Micro Top Pick

Krishna’s paper that was selected as a Top Pick is entitled “Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom.” The paper was published at the 45th International Symposium on Computer Architecture (ISCA), held June 2-6, 2018 in Los Angeles, California. Krishna’s coauthors are his recently graduated M.S. student, Aniruddh Ramrakhyani, and Paul Gratz, an ECE associate professor at Texas A&M University.

All high-performance computers today are built by connecting many processors together. These could be cores on a single-chip inside a smartphone or laptop, or servers inside a supercomputer or datacenter. A key challenge in designing the interconnection network connecting these processors is that of “deadlocks”. A deadlock is a scenario where a set of packets is stuck indefinitely and cannot move forward because they form a cyclic dependence. An analogy is that of a traffic jam in road networks where each car waits for the car in front of it to move, but no car can move if they end up forming a cycle. The traditional approaches to avoid deadlocks either restricts routes (leading to lower performance) or adds more queues (leading to more area and power). Unfortunately, paying one of these two expenses is unavoidable today since a deadlock can bring the whole system to a standstill and has to be avoided for functional correctness of any interconnection network.

In this paper, Krishna and his co-authors challenge the theoretical notion of viewing deadlocks as a resource (in this case queues) dependence problem, and view it instead as a lack of coordination between distributed packets. They demonstrate that enabling every packet to move forward at exactly the same time can help them all move forward and get out of the deadlock. Imagine the same traffic jam as before, but every car in the jam agreeing to move forward at exactly the same time to avoid any collisions. This was the first work to show a deadlock-free interconnection network with fully adaptive routing, without any routing restrictions, with only a single queue at every router port.

IEEE Micro Honorable Mention

Krishna’s paper that was selected as an Honorable Mention is entitled “MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects.” The paper was published at the 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), held March 24-28, 2018 in Williamsburg, Virginia. Krishna’s coauthors are his Ph.D. students, Hyoukjun Kwon and Ananda Samajdar.

Machine Learning (ML) and Artificial Intelligence (AI) are becoming ubiquitous. Deep Neural Networks (DNN) have demonstrated highly promising results across applications like computer vision, speech recognition, language translation, recommendation systems, and games. The computational complexity of DNNs and a need for high energy-efficiency has led to a surge in research on hardware accelerators. These AI accelerators are designed for keeping the target DNN algorithm in mind, and use custom datapaths and memory hierarchies to provide 10-1000x better performance or energy-efficiency than traditional CPUs and GPUs. Almost every major company today is building its own version of an AI accelerator. However, a key challenge today is that AI/ML algorithms are evolving at an extremely rapid rate - almost daily, while designing and taping out a hardware chip takes millions of dollars, and replacing these chips every time the algorithm changes is not practical. Thus, an open question today is how to design an accelerator chip that can be built and deployed (on smartphones and/or datacenters) and will be able to run both current and future algorithms efficiently, without having to be replaced frequently.

In their paper, Krishna and his students address this issue by adding lightweight, non-blocking, and reconfigurable interconnects within a DNN accelerator called MAERI. They demonstrate that almost any DNN model can be mapped while utilizing close to 100 percent of the accelerator’s compute resources, by simply reconfiguring the proposed interconnects appropriately. This makes the MAERI approach future-proof to innovations across DNN models and dataflow/mapping techniques.

Krishna Tapped for Google Faculty Research Award

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Tushar Krishna has been named as one of the recipients of the Google Faculty Research Award (FRA). Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE).

The Google FRA program focuses on funding world-class technical research in Computer Science, Engineering, and related fields. Among 910 proposals from 40 countries and over 320 universities submitted this year, 158 projects were selected for funding. The goal of the Google FRA is to identify and strengthen long-term collaborative relationships with faculty working on problems that will impact how future generations use technology. The award is highly competitive – only 15 percent of applicants receive funding – and each proposal goes through a rigorous Google-wide review process.

The title of Krishna’s award-winning proposal was "Using ML to Design ML Accelerators." With the end of Moore’s Law, the performance of conventional CPUs has stagnated. The growing computing demands from applications, such as Machine Learning (ML), has led to an explosion of custom hardware accelerators (across several companies and startups) for running Machine Learning algorithms at real-time latency and high energy-efficiency. 

A key challenge, however, is that the design space of these accelerators is extremely huge due to an increasing and rapidly evolving suite of Artificial Intelligence/ML models, different requirements for training vs. inference, a plethora of dataflow approaches for minimizing data movement, and varying area-power budgets depending on the target device. Krishna’s proposal seeks to enable rapid design and deployment of ML accelerators by leveraging ML algorithms to efficiently represent and search through this hardware design space.

An ECE faculty member since 2015, Krishna leads the Synergy Lab at Georgia Tech. He and his team focus on architecting next-generation intelligent computer systems and interconnection networks for emerging application areas such as machine learning. Krishna also received an NSF CISE Research Initiation Initiative Award in 2018. He recently had one of his papers selected as an IEEE Micro Top Pick from computer architecture conferences and a second paper was selected as an Honorable Mention; Krishna’s work will be acknowledged in the May/June 2019 issue of IEEE Micro.

Krishna Chosen for Facebook Research Faculty Award

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Tushar Krishna has been chosen as one of the recipients of Facebook Research's Faculty Award for AI System Hardware/Software Co-Design. Krishna was among the eight winners who were selected from 88 worldwide submissions.  

The title of Krishna’s award-winning project is “ML-Driven HW-SW Co-Design of Efficient Tensor Core Architectures.” In this project, co-design implies simultaneous design and optimization of several aspects of the system, including hardware and software, to achieve a set target for a given system metric, such as throughput, latency, power, size, or any combination these factors. 

Artificial intelligence (AI) and deep learning have been particularly amenable to such co-design processes across various parts of the software and hardware stack, leading to a variety of novel algorithms, numerical optimizations, and AI hardware. Krishna’s proposal focuses on creating an automated machine learning (ML)-driven closed-loop system to generate custom AI hardware platforms for the target algorithms and/or performance/energy constraints using a library of lego-like heterogeneous hardware building blocks.

Krishna has been an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. He and his team focus on architecting next-generation intelligent computer systems and interconnection networks for emerging application areas such as machine learning. Krishna has received a Google Faculty Research Award and an NSF CISE Research Initiation Initiative Award. He recently had one of his papers selected as an IEEE Micro Top Pick from computer architecture conferences and a second paper was selected as an Honorable Mention; Krishna’s work will be acknowledged in the May/June 2019 issue of IEEE Micro.

Krishna Named to ON Semiconductor Junior Professorship

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Tushar Krishna has been appointed to the ON Semiconductor Junior Professorship, effective September 1, 2019. A professorship for untenured faculty members in the Georgia Tech School of Electrical and Computer Engineering (ECE), this position was previously held by ECE Professor Arijit Raychowdhury. 

Krishna joined the ECE faculty in August 2015, after working as a postdoctoral researcher at MIT and a research engineer at Intel in Hudson, Massachusetts. He is a member of the Computer Systems and Software technical interest group and holds an adjunct faculty appointment with Tech’s School of Computer Science. 

Krishna’s research spans the areas of computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators. Working amongst these research areas, he and his team of seven graduate students in the Synergy Lab focus on optimizing data movement in modern computing systems. Krishna has graduated four master’s degree students and has also had several undergraduate researchers working in his lab. An excellent classroom instructor, he teaches Advanced Computer Architecture; Architecture, Concurrency, and Energy in Computation; Interconnection Networks; and Hardware Accelerators for Machine Learning.

Krishna received the B.Tech. degree in Electrical Engineering with honors from the Indian Institute of Technology Delhi in 2007, the M.S.E. degree in Electrical Engineering from Princeton University in 2009, and the Ph.D. degree in Electrical Engineering and Computer Science from MIT in 2014. 

Krishna has published more than 50 refereed journal and conference papers. In 2018, he won the NSF CISE Research Initiation Initiative Award, and in 2019, he won both the Google Faculty Research Award and Facebook Research’s Faculty Award for AI System Hardware/Software Co-Design. Earlier this year, Krishna had one of his papers selected as an IEEE Micro Top Pick and a second paper was chosen as an Honorable Mention in the May/June 2019 issue of the journal. 

Krishna’s Research to be Featured in IEEE Micro Top Picks Issue

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Tushar Krishna will have one of his recent research papers featured in the IEEE Micro “Top Picks from Computer Architecture Conferences,” to be published in the May/June 2020 issue. 

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering, where he leads the Synergy Lab. This is the second year in a row that one of Krishna’s papers has been chosen as an IEEE Micro Top Pick.

Every year, IEEE Micro publishes this special issue, which recognizes the year’s top papers in computer architecture that have potential for long-term impact. In order for a paper to be considered for a top pick, it must first have been accepted in a major computer architecture conference that year and that have acceptance rates of ~18-22%. Out of 96 submissions this year, twelve were selected as "Top Picks." 

Krishna's paper was titled "Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach.” The co-authors were his Ph.D. student Hyoukjun Kwon; Vivek Sarkar, a professor from the School of Computer Science; Sarkar's Ph.D. student Prasanth Chatarasi; and two NVIDIA collaborators, Michael Pellauer and Angshuman Parashar. 

Deep Learning is being deployed at an increasing scale—across the cloud and IoT platforms—to solve complex regression and classification problems in image recognition, speech recognition, language translation, and many more fields, with accuracy close to and even surpassing that of humans. Tight latency, throughput, and energy constraints when running Deep Neural Networks (DNNs) have led to a meteoric increase in specialized hardware–known as accelerators–to run them.

Running DNNs efficiently is challenging for two reasons. First, DNNs today are massive and require billions of computations, and secondly, DNNs have millions of inputs/weights that need to be moved from memory to the accelerator chip which consumes orders of magnitude more energy than the actual computation. DNN accelerators try to address these two challenges by mapping these computations in parallel across hundreds of processing elements to improve performance and by reusing inputs/weights on-chip across multiple outputs to improve energy efficiency. Unfortunately, there can be trillions of ways of slicing and dicing the DNN (also known as “dataflow”) to map it over the finite compute and memory resources within an accelerator.

Krishna’s paper demonstrates a principled approach and framework called MAESTRO to estimate data reuse, performance, power, and area of DNN dataflows. MAESTRO enables rapid design-space exploration of DNN accelerator architectures and mapping strategies, depending on the target DNNs or domain (cloud or IoT). MAESTRO is available as an open-source tool at http://synergy.ece.gatech.edu/tools/maestro, and it has already seen adoption within NVIDIA, Facebook, and Sandia National Labs.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Krishna Wins Facebook Research Faculty Award for Second Straight Year

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Tushar Krishna has been chosen as one of the recipients of the Facebook Research Faculty Award for AI System Hardware/Software Co-Design. Krishna was among the nine winners who were selected from 132 worldwide submissions. This is the second year in a row that Krishna has won this award.

The title of Krishna’s award-winning project is “HW/SW co-design of next-generation training platforms for DLRMs.” DLRMs stand for Deep Learning Recommendation Models and are used within online recommendation systems, such as ranking of search queries in Google, friend suggestions on Facebook, and job advertisements from LinkedIn. DLRMs are very different from Deep Learning models used for computer vision and natural language processing as they involve both continuous (or dense) features and categorical (or sparse) features. For example, the date and time for clicks on a webpage by a user can be used as dense features, while the representation of the user based on all the webpages visited by him/her in the past 48 hours can be used as sparse features for training recommendation models. The dense features are processed with multilayer perceptrons (MLPs) while the sparse features are processed using a technique called embeddings.

Training DLRMs constitutes more than 50 percent of the training demand in companies like Facebook. This is because storing the embeddings requires significant memory capacity, on the order of 100s of gigabytes to a few terabytes, which is more than the memory available on a single accelerator (GPU or TPU) node. Thus, DLRMs require clever partitioning and distribution of the model across multiple accelerator nodes. This naturally makes it crucial to optimize the communication between these nodes to reduce overall training time.

As part of the award, Krishna will explore mechanisms for efficient distributed training of recommendations models. The research will develop techniques involving co-design across software and hardware to enable scalability across 100s-1000s of accelerator nodes. The research effort will leverage ASTRA-sim, a distributed DL training simulator developed by Krishna and his Ph.D. student Saeed Rashidi in collaboration with Facebook and Intel.

Krishna is an assistant professor in the School of Electrical and Computer Engineering at Georgia Tech. He also holds the ON Semiconductor Junior Professorship. Krishna has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E. in Electrical Engineering from Princeton University (2009), and a B.Tech. in Electrical Engineering from the Indian Institute of Technology, Delhi (2007). Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and three have won best paper awards. He received the National Science Foundation CRII award in 2018 and both a Google Faculty Award and a Facebook Faculty Award in 2019.

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