Calhoun Elected as OHBM Fellow

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Vince Calhoun

Vince Calhoun has been elected as a Fellow of the Organization of Human Brain Mapping (OHBM). OHBM is an international society dedicated to using neuroimaging to discover the organization of the human brain.

Calhoun is the Distinguished University Professor of Psychology at Georgia State University. He is the director of the Center for Advanced Brain Imaging, a joint venture between Georgia State University and Georgia Tech. Calhoun is also the founding director of the Center for Translational Research in Neuroimaging and Data Science, a tri-institutional effort supported by Georgia State, Georgia Tech, and Emory University to increase cooperation among Atlanta brain imaging researchers.

Calhoun is a Georgia Research Alliance (GRA) Eminent Scholar in Neuroscience and Neuroinformatics, and he also holds appointments in the School of Electrical and Computer Engineering at Georgia Tech and in neurology and psychiatry at Emory University School of Medicine. His research is focused on developing new ways to analyze and use complex brain imaging data by drawing on advanced machine-learning approaches.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

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Jackie Nemeth

School of Electrical and Computer Engineering

Khan Chosen for DARPA Young Faculty Award

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Asif Khan

Asif Khan has been chosen for a DARPA Young Faculty Award. Khan is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he has been on the faculty since 2017.

Khan is receiving this award for his research on ferroelectric field-effect transistors for embedded non-volatile memory applications. Ferroelectric field-effect transistors is one of the most-promising device technologies for artificial intelligence (AI) and machine learning (ML) hardware, due to its energy efficiency and compatibility with high-volume semiconductor manufacturing. The project will focus on solving the critical voltage problem of this device technology, by identifying and implementing new strategies for interface defect reduction in and the downscaling of the ferroelectric gate-dielectric stack. 

Khan works on advanced semiconductor devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for AI/ML/data-centric applications.

His early career work led to the first experimental proof-of-concept demonstration of a physical phenomenon, namely the negative capacitance, in ferroelectric materials, which can reduce the power dissipation in electronic devices below the “fundamental” thermodynamic limit. Negative capacitance is currently a vibrant research area in materials science, condensed matter physics, and electrical engineering, and it is being pursued by all major semiconductor companies for advanced transistor technologies.

In the past, Khan has received multiple awards, including the NSF CAREER Award (2021), the Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). He was also named to the Center for Teaching and Learning Class of 1934 CIOS Honor Roll for his outstanding teaching in ECE8863 Quantum Computing Devices and Hardware in Fall 2020.

Khan’s group currently consists of seven graduate students and two research staff members. They publish in flagship microelectronics conferences, such as the International Electron Devices Meeting (IEDM) and the Symposium on VLSI Technology, and in journals including IEEE Electron Device LettersIEEE Transactions on Electron DevicesNature ElectronicsNature Materials, and Nano Letters. His students received multiple international and Institute-level awards, including the IEEE EDS Masters Student Fellowship (Prasanna Ravindran, 2020) and the Georgia Tech ECE's Colonel Oscar P. Cleaver Award (Nujhat Tasneem in 2018 and Zheng Wang in 2017) for achieving the highest score on the ECE Ph.D. preliminary examination, which was the criteria for the award up to 2018.

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

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Jackie Nemeth

School of Electrical and Computer Engineering

Khan Wins NSF CAREER Award

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Asif Khan

Asif Khan has been named as a recipient of the NSF CAREER Award. He is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and also holds a courtesy appointment in the School of Materials Science and Engineering.

The title of Khan’s award is “Antiferroelectric Negative Capacitance Transistors for Ultra-low Power Computing,” and it will start on March 15, 2021 and end on February 28, 2026. 

Today's society is experiencing an unprecedented growth of its digital footprint – be it in the form of uploading a photo on Facebook, live-streaming a teaching module to a massive global audience on YouTube, or commandeering a revolution via Twitter. This convenience of modern computing, however, comes with a steep cost in terms of energy use and environmental impact. Today, the global information infrastructure, such as data centers, emit as much greenhouse gases as that of the state of Nevada or a country, such as The Netherlands or Malaysia, and constitute around 1 percent of world-wide electricity demand. According to scientific estimates, this fraction may increase to a double digit percentage in the next 15-20 years. 

At the core of this predicament lies the fact that the fundamental building blocks of digital hardware – the transistors – have long been overdue for a prime upgrade in terms of their energy efficiencies. The proposed research aims to explore an energy-efficient transistor concept – known as a negative capacitance field-effect transistor, using a new class of materials called antiferroelectric oxides. 

Khan joined the ECE faculty in 2017. His research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His research group currently focuses on ferroelectric devices, in all aspects ranging from materials physics, growth, and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/data-centric applications. Khan’s Ph.D. work led to the proof-of-concept demonstration of the negative capacitance phenomenon in ferroelectric materials, which can reduce the power dissipation in electronic devices below the ‘fundamental’ thermodynamic limit. This culminated in the initial development of the field of negative capacitance.

Khan has published 2 book chapters and 70 journal and peer-reviewed conference publications, and he has given 20 invited talks and tutorials at premier microelectronics and ferroelectric conferences. Khan currently has one patent pending at Intel. 

Khan’s awards include the NSF CAREER award (2021), Intel Rising Star Award (2020), Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011), and the University Gold Medal from Bangladesh University of Engineering and Technology (2011). His group at Georgia Tech consists of six Ph.D. students and three research engineers, many of whom won Institute-level and international awards, including an IEEE Electron Devices Society (EDS) Masters Student Fellowship (2020). Khan’s research is supported by the National Science Foundation, the Defense Advanced Research Projects Agency, the Semiconductor Research Corporation, and Intel Corporation. 

Khan has also developed a graduate course, ECE 8863A Quantum Computing Devices and Hardware, as a part of the campus wide response to the national prioritization of quantum computing, known as the National Quantum Initiative Act (NQIA) that was signed by the U.S. president in 2018. Khan recently received the Class of 1934 CIOS Honor Roll award for excellence in teaching this course in Fall 2020. 

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

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Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Calhoun Chosen for SIRS Honorific Award

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Vince Calhoun

Vince Calhoun has been named as the recipient of the 2021 Honorific Award for Outstanding Translational Research from the Schizophrenia International Research Society (SIRS). Calhoun will receive this award on April 17 during the SIRS annual meeting, which will be held virtually this year.

Calhoun is being recognized as an internationally renowned research scholar in the development and use of advanced neuroimaging approaches to study the biological underpinnings of schizophrenia. According to his nomination, Calhoun is a pioneer in the fields of data-driven brain connectivity, dynamic connectivity, and multimodal data fusion, and he has been a key visionary in the development of neuroimage-based markers of brain health and disorder. 

Then nomination goes on to say that Calhoun has shown an impressive ability to build a bridge between the development of advanced algorithms and their extensive application. He has been a leader in open science, making these technologies available to all in the field through multiple software tools, tutorials, and training workshops. 

Calhoun is a Georgia Research Alliance (GRA) Eminent Scholar in Neuroscience and Neuroinformatics, and he also holds appointments in the School of Electrical and Computer Engineering at Georgia Tech and in neurology and psychiatry at Emory University School of Medicine. He is the founding director of the Center for Translational Research in Neuroimaging and Data Science (TReNDS), a tri-institutional effort supported by Georgia State University, Georgia Tech and Emory to increase cooperation among Atlanta brain imaging researchers. He is also the founder of the Center for Advanced Brain Imaging, a joint venture between Georgia State and Georgia Tech. 

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Yu Appointed as IEEE CASS Distinguished Lecturer

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Shimeng Yu has been named as a Distinguished Lecturer for the IEEE Circuits and Systems Society (CASS) for 2021-2022. Yu is an associate professor in the Georgia Tech School of Electrical and Computer Engineering (ECE).

Yu leads the Laboratory for Emerging Devices and Circuits, where he and his team design energy-efficient computing systems based on emerging nanoelectronic devices. An example of his group’s work is the development of hardware accelerators for machine/deep learning with CMOS and beyond CMOS technologies.

The two areas in which Yu will present lectures include:

  • Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Inference Engine
  • NeuroSim: A Benchmark Framework of Compute-in-Memory Hardware Accelerators from Devices/Circuits to Architectures/Algorithms

Yu has been a member of the ECE faculty since 2018. Prior to joining Georgia Tech, he was on the ECE faculty at Arizona State University for five years. Yu has received numerous awards over the last several years, including the ACM/IEEE Design Automation Conference 40 Under-40 Innovators Award, Semiconductor Research Corporation Young Faculty Award, ACM Special Interest Group on Design Automation Outstanding New Faculty Award, and IEEE Electron Devices Society Early Career Award. 

Yu has been active in IEEE CASS activities, including serving on the technical committee of Nanoelectronics and Gigascale Systems and the review committee of the IEEE International Symposium on Circuits and Systems (ISCAS). He currently serves as the associate editor of the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC). More information on IEEE CASS can be found at https://ieee-cas.org/

Location

Atlanta, GA

Email

jackie.nemeth@ece.gatech.edu

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

 

Khan Recognized with 2020 Intel Rising Star Award

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Asif Khan has been named as one of the 10 awardees of the 2020 Intel Rising Star Award. Khan is an assistant professor at the Georgia Tech School of Electrical and Computer Engineering (ECE).

The purpose of the program is to help promote the careers of early career faculty members who show great promise as future academic leaders in disruptive computing technologies and to foster long term collaborative relationships with Intel. The awards were given based on progressive research in computer science, engineering, and social science in support of the global digital transition in the following areas: software, security, interconnect, memory, architecture, and process.

Khan joined the ECE faculty in 2017, with a courtesy appointment with the School of Materials Science and Engineering. He received his Ph.D. in electrical engineering and computer sciences from the University of California, Berkeley in 2015.

Khan’s research is on advanced semiconductor devices—devices that will shape the future of computing in the post-scaling era. His group is currently focusing on ferroelectric devices on all aspects ranging from materials physics, growth and electron microscopy to device fabrication, all the way to ferroelectric circuits and systems for artificial intelligence/machine learning/variable load applications. 

His research group consists of five graduate students and two research staff members. They publish in venues such as the International Electron Devices Meeting, the Symposium on VLSI Technology and CircuitsIEEE Electron Device Letters, IEEE Transactions on Electron Devices, Nature Electronics, Nature Materials, Nano Letters, and Nature.

Khan’s program is supported by the National Science Foundation, the Semiconductor Research Corporation, and the Defense Advanced Research Program Agency. His Ph.D. research led to the first experimental demonstration of the negative capacitance effect in ferroelectrics, which can reduce the energy dissipation in CMOS technology below the fundamental thermodynamic (Boltzmann) limit. One of his publications was cited as one of the nine significant papers in the history of ferroelectricity in a 2020 editorial article in Nature Materials, celebrating the 100th year since the discovery of ferroelectricity in 1920.

Four Georgia Tech Faculty Named IEEE Fellows

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Jaydev Desai
Four Georgia Tech faculty members were named IEEE Fellows, effective January 1, 2018. They are Jaydev Desai, a professor in the Wallace H. Coulter Department of Biomedical Engineering (BME); Saibal Mukhopadhyay and Justin Romberg, both professors in the School of Electrical and Computer Engineering (ECE); and Kevin James “Jim” Sangston, a senior research engineer in the Georgia Tech Research Institute (GTRI).
Saibal Mukhopadhyay has been an assistant professor in ECE since 2007.
Kevin James "Jim" Sangston

Four Georgia Tech faculty members were named IEEE Fellows, effective January 1, 2018. They are Jaydev Desai, a professor in the Wallace H. Coulter Department of Biomedical Engineering (BME); Saibal Mukhopadhyay and Justin Romberg, both professors in the School of Electrical and Computer Engineering (ECE); and Kevin James “Jim” Sangston, a senior research engineer in the Georgia Tech Research Institute (GTRI).

The IEEE Grade of Fellow is conferred by the IEEE Board of Directors upon a person with an outstanding record of accomplishments in any of the IEEE fields of interest. IEEE Fellow is the highest grade of membership and is recognized by the technical community as a prestigious honor and an important career achievement.

Desai is being recognized “for contributions to medical and swarm robotics.” A BME faculty member since 2016, he also serves as associate director of the Institute for Robotics and Intelligent Machines and as director of the newly launched Georgia Center for Medical Robotics. Desai’s research interests are primarily in image-guided surgical robotics, cancer diagnosis at the micro-scale, and rehabilitation robotics. Before joining Georgia Tech, Desai was a professor in the Department of Mechanical Engineering at the University of Maryland, College Park.

Mukhopadhyay is being recognized “for contributions to energy-efficient and robust computing systems design.” An ECE faculty member since 2007, he leads the Gigascale Reliable Energy Efficient Nanosystem (GREEN) Lab, where he and his current team of 12 Ph.D. students develop smart machines that are able to generate usable information from real-time data for diverse applications - from self-powered sensors to mobile phones to high-performance servers. Mukhopadhyay’s team explores algorithmic principles to make these systems energy-efficient, robust, and secure, and pursue their experimental demonstration in silicon. 

Romberg is being recognized “for contributions to compressive sensing.” An ECE faculty member since 2006, he is the School’s associate chair for Research and holds the Schlumberger Professorship. In addition, Romberg serves as associate director for the Center for Machine Learning. He conducts research that is on the interface between signal processing, applied harmonic analysis, and optimization. Romberg and his current team of six Ph.D. students are interested in both the mathematical theory and real-world implementation of algorithms to make difficult processing tasks much easier.

Sangston is being recognized “for contributions to coherent detection of radar signals in clutter.” He initially came to GTRI from the U.S Naval Research Laboratory in 1996. His research in target detection in difficult clutter environments from the mid-1990s up till the present time has been a fruitful source of ideas and motivation for many investigators pursuing advanced research on radar target detection problems throughout the world. He currently works in the Sensors and Electromagnetic Applications Laboratory (SEAL), where he conducts research that seeks to combine advanced geometric and algebraic ideas to solve challenging radar signal processing problems. 

The IEEE is the world’s leading professional association for advancing technology for humanity. Through its 400,000-plus members in 160 countries, the association is a leading authority on a wide variety of areas ranging from aerospace systems, computers and telecommunications to biomedical engineering, electric power, and consumer electronics.

Dedicated to the advancement of technology, the IEEE publishes 30 percent of the world’s literature in the electrical and electronics engineering and computer science fields, and has developed more than 1,300 active industry standards.  The association also sponsors or co-sponsors nearly 1,700 international technical conferences each year.  To learn more about IEEE or the IEEE Fellow Program, please visit www.ieee.org.

Krishna Selected for NSF CRII Award

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Tushar Krishna has been selected for a National Science Foundation (NSF) CISE Research Initiation Initiative Award.

Krishna is an assistant professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he leads the Synergy Lab. This two-year-long NSF award will support his project entitled “Enabling Neuroevolution in Hardware.”

Over the past few years, machine learning algorithms, especially neural networks (NN) have seen a surge of popularity owing to their potential in solving a wide variety of complex problems across image classification and speech recognition. Unfortunately, in order to be effective, NNs need to have the appropriate topology (connections between neurons) for the task at hand and have the right weights on the connections. This is known as supervised learning and requires training the NN by running it through terabytes to petabytes of data.

This form of machine learning is infeasible for the emerging domain of autonomous systems (robots/drones/cars) which will often operate in environments where the right topology for the task may be unknown or is constantly changing, and robust training data is not available. Autonomous systems need the ability to mirror human-like learning, where we are continuously learning, and often from experiences rather than being explicitly trained. This is known as reinforcement learning.



The focus of Krishna’s research will be on neuroevolution (NE), a class of reinforcement learning algorithms that evolve NN topologies and weights for the task at hand using evolutionary algorithms. The goal of this project will be on enabling NE in energy-constrained autonomous devices by leveraging opportunities for parallelism and hardware acceleration. If successful, this research could enable mass proliferation of autonomous drones and robots that can learn to perform tasks without being explicitly trained.

EDA’s CAEML Grows More Humps: Al Expands Role in Design

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John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the Center for Co-Design of Chip, Package, System (C3PS), Georgia Tech.

The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.

Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.

“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”

Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.

After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.

Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."

Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).

“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”

https://www.eetimes.com/document.asp?doc_id=1332917

Aneeq Zia Awarded IPCAI 2018 Young Investigator Travel Award

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Aneeq Zia, a third-year electrical and computer engineering Ph.D. student at Georgia Tech, was recently awarded the Young Investigator Travel Award at the  9th International Conference on Information Processing in Computer-Assisted Interventions (IPCAI) in Berlin, Germany. Zia was one of three authors selected for the award, which comes with a $1,000 prize.

The winners were selected by senior members of the IPCAI committee based on scientific excellence and innovation.

Zia was recognized for his work on his paper, Automated Surgical Skills Assessment in RMIS Training. His research focuses on exploiting the fluency of surgical motions in order to perform automated surgical skills assessments. This helps minimize the amount of time that expert surgeons spend manually inputting feedback into basic robot-assisted minimally invasive (RMIS) training, while also making their feedback more objective.

“I’m really glad to have received this award. Considering I was the only one presenting at this conference from Georgia Tech this year, I think getting this award gives a great impression of the institute and our work,” said Zia.

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Atlanta, GA

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allison.blinder@cc.gatech.edu

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Allie Blinder

Communications Officer 

allison.blinder@cc.gatech.edu

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